NAND Interface with Independent I/O Periods for Parallel Memory Dies
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Solution Overview
Problem
Existing semiconductor systems face performance degradation due to increased command overhead in NAND interfaces, especially as operating frequencies increase, and parallel operations of NAND flash memory devices are difficult to perform effectively.
Innovation Solution
A semiconductor system with a first and second semiconductor apparatus, where the first apparatus provides chip enable and command address signals to the second apparatus, allowing independent data input/output periods for multiple memory dies through separate command address signal sets, enabling parallel operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If NAND interface method transmits command address signal and data through the same input/output bus, then device complexity is reduced, but command overhead increases causing performance degradation
Solution Approach 1:
The patent segments the interface into separate command address bus and data bus, allowing independent transmission paths. This segmentation reduces command overhead by enabling parallel command and data operations, directly resolving the performance degradation issue while maintaining reasonable device complexity through modular bus structure
Solution Approach 2:
The patent introduces a time dimension to the interface operation by implementing separate command address and data transmission phases. This temporal dimensionality change allows the system to overcome the limitation of single-bus sequential operations, improving productivity without significantly increasing spatial complexity
2Productivity
If separate command address (SCA) interface method transmits command address signal and data through different input/output buses, then command overhead decreases, but parallel operations of multiple NAND flash memory devices become difficult
Solution Approach 1:
The patent implements a universal bus structure where the data bus can serve multiple memory devices simultaneously through independent chip select signals. Each memory device has its own chip select signal, allowing the same data bus to be universally accessed by multiple devices in parallel, thereby improving adaptability while maintaining the productivity benefits of separate command address transmission
Solution Approach 2:
The patent introduces chip select signals as intermediary control signals that mediate between the separate command address bus and multiple memory devices. These intermediary signals enable parallel operation capability by selectively activating specific memory devices during data transmission, resolving the limitation of the SCA interface method
3Speed
If operating frequency of NAND flash memory system increases, then data transmission speed improves, but command overhead increases causing performance degradation
Solution Approach 1:
The patent ensures continuous useful action by enabling overlapping command and data operations through separate buses. While data transmission occurs at high speed, command operations can proceed simultaneously without waiting for data cycles to complete, maintaining system performance at high operating frequencies by eliminating idle time and ensuring continuous productive operation
Data Source
AI summary
A semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. The first semiconductor apparatus provides the second semiconductor apparatus with a chip enable signal and a command address signal set, and the second semiconductor apparatus performs an internal operation based on the chip enable signal and the command address signal set. The first semiconductor apparatus provides the second semiconductor apparatus with a selection chip enable command, and the second semiconductor 10 apparatus transmits data to the first semiconductor apparatus or receives the data from the first memory device after receiving the selection chip enable command.