NAND IO Interface for SLC-to-PLC Copyback Cycle Reduction
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Solution Overview
Problem
The existing interface for NAND memory devices, particularly in multi-level cell (MLC) systems like TLC, QLC, and PLC, is complex and inefficient, requiring numerous command-address-data cycles for copyback program operations, limiting system performance and adding complexity to system hardware/firmware.
Innovation Solution
An enhanced IO interface that utilizes two set-feature latches to store SLC start page and block addresses, enabling an enhanced mode that reduces the number of command-address-data cycles from 78 to 25 by internally pre-reading and copying data from SLC blocks to PLC blocks using static page buffers, simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the existing interface is used for copyback program operations in PLC systems, then data can be moved from SLC blocks to PLC blocks, but the number of command-address-data cycles increases significantly (up to 86 cycles), limiting system performance
Solution Approach 1:
The patent applies preliminary action by pre-reading all five SLC pages (LP, UP, XP, TP, EP) into the page buffer before initiating the copyback program operation. This allows the controller to have all necessary data ready in advance, eliminating the need for sequential read operations during the program cycle, thereby reducing the total command-address-data cycles from 86 to 25 cycles.
Solution Approach 2:
The patent merges multiple separate operations into a single streamlined process. By combining the read operations for all five SLC pages with the program operation for PLC blocks into a unified enhanced IO interface sequence, the patent reduces the total number of cycles. The enhanced IO interface merges the read-and-program operations that would otherwise be executed as separate sequential steps.
2Reliability
If the existing interface manages copyback operations atomically, then data integrity is maintained, but hardware and firmware complexity increases significantly
Solution Approach 1:
The patent applies self-service by enabling the NAND device to automatically manage the copyback operation without requiring complex external control. The enhanced IO interface allows the device to self-coordinate the read-and-program sequences, automatically handling data integrity through its internal control logic rather than requiring complex external atomic management mechanisms.
Solution Approach 2:
The patent changes the operational parameters by introducing an enhanced IO interface mode that modifies how commands are executed. By changing the interface parameters and operation sequences, the patent achieves simplified atomic management while maintaining data integrity, reducing hardware/firmware complexity compared to traditional approaches.
3Quantity of substance
If all five SLC pages are read and copied to PLC blocks sequentially, then complete data transfer is achieved, but the operation time increases due to multiple command sequences
Solution Approach 1:
The patent applies preliminary action by pre-reading all five SLC pages into the page buffer before initiating the copyback program operation. This allows the controller to have all necessary data ready in advance, eliminating the need for sequential read operations during the program cycle, thereby reducing the total command-address-data cycles from 86 to 25 cycles.
Data Source
AI summary
Methods and apparatus for Enhanced IO Interface for PLC program and program-suspend-resume operations. A NAND memory device includes blocks of single-level cell (SLC) memory and multi-level cell (MLC) memory storing n-bits per cell such as quad-level cell (QLC) or penta-level cell (PLC) memory. The NAND memory device further includes a plurality of page buffer latches and logic to copy data from a set of n SLC pages in a block of SLC memory into n respective page buffer latches and copy data from the respective page buffer latches to an MLC page (e.g., QLC or PLC page) in a block of MLC memory. These operations can be extended for NAND memory devices having multiple planes with blocks of SLC and QLC/PLC memory. QLC/PLC program and program-resume operations are supported with optional ECC correction operations.