NAND Flash Isolation Cut-Outs for Read Accuracy
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Solution Overview
Problem
Interference from neighboring devices or areas can cause errors when reading data stored in non-volatile storage devices, such as flash memory, due to charge coupling effects between floating gates, control gates, and channel regions.
Innovation Solution
A non-volatile storage device structure is fabricated with isolation regions that form concave cut-out shapes in the substrate, allowing floating gates to hang over these sections, creating a fringe electric field that shields the channel from unwanted capacitive effects and dominates over neighboring structures, reducing interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar isolation regions are used, then manufacturing is simpler, but interference from neighboring devices causes read errors
Solution Approach 1:
The isolation region is divided into two distinct sections: a first section that extends horizontally between adjacent active areas and a second section that extends vertically beneath the floating gate. This segmentation creates a three-dimensional isolation structure that effectively blocks charge coupling paths from neighboring devices while maintaining manufacturing feasibility through sequential etching processes.
Solution Approach 2:
The isolation structure transitions from a conventional two-dimensional planar region to a three-dimensional configuration by adding the vertical second section beneath the floating gate. This dimensional extension creates a deeper isolation barrier that intercepts charge coupling paths from adjacent floating gates and control gates, thereby reducing interference without significantly complicating the manufacturing process.
2Area of stationary object
If floating gates are positioned closer to substrate, then device area is reduced, but charge coupling interference increases
Solution Approach 1:
The isolation structure acts as an intermediary element positioned between the floating gate and neighboring charge storage regions. By placing the second section of the isolation region directly beneath the floating gate, it serves as a charge-blocking intermediary that prevents capacitive coupling from adjacent devices, allowing the floating gate to be positioned closer to the substrate without increasing interference.
3Reliability
If deeper isolation regions are created, then shielding effect is improved, but manufacturing complexity increases
Solution Approach 1:
The first section of the isolation region is formed first using isotropic etching, creating a preliminary isolation structure between active areas. Subsequently, the second vertical section is added using anisotropic etching to extend the isolation beneath the floating gate. This preliminary action approach allows the deeper isolation structure to be built incrementally, maintaining manufacturing ease while achieving effective shielding.
Solution Approach 2:
The manufacturing process utilizes two distinct etching parameters: isotropic etching for the horizontal first section and anisotropic etching for the vertical second section. By changing the etching parameters appropriately for each section, the patent achieves the desired three-dimensional isolation structure with controlled precision, balancing manufacturing ease with isolation effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively reduces errors during read operations by shielding the channel from neighboring influences, ensuring accurate data retrieval and storage.
Implementation Method 1
creating a fringe electric field that shields the channel from unwanted capacitive effects
Implementation Method 2
The threshold voltage of the transistor is controlled by the amount of charge that is retained in the charge storage region
Data Source
AI summary
Shallow trench isolation regions are positioned between NAND strings (or other types of non-volatile storage). These isolation regions include sections that form concave cut-out shapes in the substrate for the NAND string (or other types of non-volatile storage). The floating gates (or other charge storage devices) of the NAND strings hang over the sections of the isolation region that form the concave cut-out shape in the substrate. To manufacture such a structure, a two step etching process is used to form the isolation regions. In the first step, isotropic etching is used to remove substrate material in multiple directions, including removing substrate material underneath the floating gates. In the second step, anisotropic etching is used to create the lower part of the isolation region.