NAND-Resident L2P Mapping for DRAM-Limited Flash Translation
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Solution Overview
Problem
The increasing density of NAND memory cells necessitates larger logical-to-physical (L2P) tables, which in turn requires more dynamic random-access memory (DRAM) resources, leading to infeasible hardware layouts and performance issues.
Innovation Solution
Storing the primary L2P table in a NAND memory device, particularly in a SLC portion, while using a secondary FTL with a smaller indirection unit size and a read cache in DRAM to manage cache misses, reducing DRAM footprint and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND cell densities are increased, then storage capacity is improved, but L2P table size increases requiring larger DRAM which is infeasible due to hardware layout constraints
Solution Approach 1:
The patent transitions from storing the entire L2P table in DRAM to a hierarchical structure where a secondary L2P table is stored in NAND memory and a primary L2P table is maintained in a small DRAM cache. This dimensional change in storage hierarchy allows the system to scale with NAND density without proportionally increasing DRAM requirements, resolving the contradiction between storage capacity and DRAM size.
Solution Approach 2:
The patent implements a nested L2P table structure where the secondary L2P table (stored in NAND) contains mappings to the primary L2P table (stored in DRAM cache). This nested arrangement allows the system to manage large address spaces with minimal DRAM by having the NAND-stored secondary table indirect through the small DRAM-stored primary table, thus resolving the space constraint.
2Adaptability or versatility
If mapping indirection size is increased, then L2P table coverage is improved, but performance and endurance are degraded
Solution Approach 1:
The patent divides the L2P table functionality into two segmented components: a secondary L2P table in NAND with fine-grained indirection units for comprehensive coverage, and a primary L2P table in DRAM cache for fast access. This segmentation allows the system to achieve both wide coverage and high performance, as each segment can be optimized for its specific function without compromising the other.
3Ease of manufacture
If DRAM footprint is reduced, then hardware layout feasibility is improved, but L2P table storage capability is degraded
Solution Approach 1:
The patent introduces a secondary L2P table stored in NAND memory as an intermediary structure that maps logical addresses to physical locations in the primary L2P table (stored in DRAM). This intermediary allows the system to maintain large L2P table storage capability while using minimal DRAM, as the secondary table in NAND provides the bulk storage function without requiring large DRAM capacity.
4Productivity
If cache miss rates are decreased, then data access performance is improved, but cache complexity increases
Solution Approach 1:
The patent implements a read cache that pre-loads and caches portions of the primary L2P table before they are needed for actual data access operations. By performing this preliminary caching action, the system reduces cache miss rates during subsequent data access operations without requiring complex real-time cache management, as the caching is proactively performed in advance.
Data Source
AI summary
A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.