Managed NAND Host-Cached L2P Validation for Secure Fast Access
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Solution Overview
Problem
Current host-cached L2P techniques in memory devices are vulnerable to data corruption and unauthorized modifications due to the host's control of translation tables, lacking effective data validation and protection mechanisms.
Innovation Solution
Implement a verification mechanism using logical and physical address pairs, combined with encryption and sequence numbers, to validate host requests and protect proprietary operations, ensuring data integrity and preventing unauthorized modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If host-cached L2P techniques are implemented to improve performance, then data access speed is improved, but data integrity and security are compromised due to vulnerability of translation tables
Solution Approach 1:
The system implements verification mechanisms where the memory device sends feedback signals to the host about the validity and currency of L2P table entries. The host receives status information indicating whether translation table entries are current or expired, allowing it to decide whether to trust and use those entries for direct address access or fall back to traditional lookup methods.
Solution Approach 2:
The memory device performs preliminary actions by proactively notifying the host about changes to translation table entries and by pre-establishing verification mechanisms before data access operations occur. This includes the memory device monitoring its own translation tables and preparing status information to communicate with the host in advance of actual data access.
2Productivity
If host controls translation tables to enable host-cached L2P, then performance is improved, but unauthorized modifications and replay attacks become possible
Solution Approach 1:
The system introduces intermediary verification mechanisms between the host and memory device. These intermediaries include verification codes, status signals, and controlled notification protocols that mediate the relationship between host-cached translation tables and the actual memory operations, preventing direct unauthorized modifications while maintaining performance benefits.
Solution Approach 2:
The system applies preliminary anti-action by implementing verification mechanisms that detect and prevent unauthorized modifications before they can affect data integrity. The memory device proactively verifies the validity of translation table entries and can reject or correct unauthorized changes, counteracting potential malicious or erroneous host actions.
3Reliability
If internal translation tables are used exclusively to ensure data security, then data protection is improved, but performance is reduced due to lack of host acceleration
Solution Approach 1:
The system dynamically adapts its operation mode based on the trust status of host-provided translation table entries. When entries are verified as current and valid, the system uses host-cached L2P for fast access. When entries are marked as expired or invalid, the system automatically falls back to internal translation table lookups, creating a dynamic performance-protection balance.
Solution Approach 2:
The system applies partial action by using host-cached L2P only for the portion of data access that can be safely accelerated based on verification status, rather than applying it universally. This allows performance optimization for trusted entries while maintaining security for unverified or expired entries through traditional internal tables.
Data Source
AI summary
Devices and techniques for host accelerated operations in managed NAND devices are described herein. A host logical-to-physical (L2P) table of the NAND device has an associated map. Entries in the map correspond to one or more logical addresses (LA) and indicate whether the host L2P table is current for those LAs. If the table is not current, then a request will bypass the host L2P table, using a standard device L2P lookup instead. Otherwise, the host L2P table can be used.