NAND Memory Leakage Current Reduction via Drain Select Gate Biasing
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in reducing power consumption and improving performance, particularly during programming and sense operations, due to significant leakage current issues.
Innovation Solution
The solution involves biasing the drain select gates of selected and unselected blocks in a memory device using specific voltage levels, with the unselected blocks having their drain select gates floated or biased at a non-zero optimal voltage, minimizing leakage current and optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If drain select gates of unselected blocks are biased at zero voltage, then device complexity is reduced, but leakage current increases significantly
Solution Approach 1:
The patent applies parameter changes by transitioning the drain select gate voltage of unselected blocks from zero voltage to a non-zero optimal voltage level. This parameter change reduces leakage current through the drain select gate while maintaining manageable device complexity, as the voltage level can be controlled through existing transfer transistor mechanisms.
Solution Approach 2:
The patent implements preliminary action by pre-biasing the drain select gates of unselected blocks to an optimal non-zero voltage level before programming operations begin. This preliminary voltage application minimizes leakage current from the start, preventing harmful effects rather than addressing them after they occur.
2Loss of energy
If drain select gates of unselected blocks are floated, then power consumption is reduced, but leakage current increases
Solution Approach 1:
The patent resolves this contradiction by changing the voltage parameter of drain select gates in unselected blocks from zero or floating to a specific non-zero optimal voltage. This optimal voltage level reduces leakage current while the associated transfer transistors are controlled to minimize power consumption, achieving both goals simultaneously.
3Productivity
If programming voltage is applied to control gates, then storage elements are programmed, but leakage current increases in unselected blocks
Solution Approach 1:
The patent applies local quality by implementing different voltage biasing strategies for selected and unselected blocks. While selected blocks receive full programming voltage for high-speed operation, unselected blocks have their drain select gates biased at an optimal non-zero voltage to minimize leakage current, allowing each region to operate with locally optimized characteristics.
Solution Approach 2:
The patent uses preliminary action by pre-establishing optimal voltage biasing on drain select gates of unselected blocks before programming operations commence. This preliminary configuration prevents leakage current generation during programming, allowing full programming voltage to be applied to selected blocks without concern for unselected block interference.
Data Source
AI summary
A memory device with reduced leakage current during programming and sense operations, and a method for operating such a memory device. In a non-volatile memory device, current leakage at the drain select gates of NAND strings can occur in unselected blocks when a selected block undergoes a program or read operation, and the bit lines are shared by the blocks. In one approach, in which a common transfer gate driver is provided for both blocks, the drain select gates are pre-charged at an optimum level, which minimizes leakage, and subsequently floated while a program or read voltage is applied to a selected word line in the selected block. In another approach, a separate transfer gate driver is provided for the unselected block so that the optimal select gate voltage can be driven in the unselected block, even while the program or read voltage is applied in the selected block.