3D NAND Local Bit Line Layout for Read Speed at High Word-Line Counts
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Solution Overview
Problem
Current three-dimensional stacked NAND flash memory technologies face challenges in maintaining read operation performance as the number of stacked word lines increases, leading to decreased cell current and significant slowdowns due to limited silicon mobility and load capacitance.
Innovation Solution
The proposed solution involves a non-volatile semiconductor memory device with a novel configuration that includes multiple interconnect layers, memory pillars, and local bit lines, allowing for the stacking of up to 2000 word lines while maintaining effective read operation performance by optimizing silicon mobility and reducing coupling noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked word lines is increased to enhance memory capacity, then memory capacity is improved, but read operation performance deteriorates due to decreased cell current and increased load capacitance
Solution Approach 1:
The bit line is divided into multiple local bit lines, each serving a subset of memory cell strings. This segmentation reduces the load capacitance on each local bit line, allowing faster charging/discharging operations while maintaining high memory capacity through increased word line stacking. The segmentation enables parallel operation of multiple local bit lines, preserving read performance despite higher overall memory density.
Solution Approach 2:
The patent transitions from a two-dimensional bit line architecture to a three-dimensional structure with multiple interconnect layers stacked vertically. Local bit lines are arranged in different vertical layers (first, second, third interconnect layers), enabling spatial separation of signal paths and reducing coupling noise while maintaining high memory capacity through increased stacking of word lines.
2Ease of manufacture
If the number of stacked word lines is increased to reduce cost per gigabyte, then manufacturing cost is reduced, but silicon mobility decreases leading to operation slowdowns
Solution Approach 1:
By segmenting the bit line into multiple local bit lines across different interconnect layers, the patent reduces the effective load capacitance that silicon carriers must charge/discharge. This segmentation maintains operation speed by reducing the time constant (τ = RC) even as word lines are stacked to increase capacity and reduce cost.
Solution Approach 2:
The local bit lines act as intermediary conductors between the memory cell strings and the main bit line structure. These local bit lines in different vertical layers provide intermediate signal transmission paths, reducing the direct load on individual silicon-based charge paths and mitigating mobility degradation effects.
3Quantity of substance
If more word lines are stacked to increase memory capacity, then memory capacity is improved, but coupling noise between bit lines increases
Solution Approach 1:
The patent vertically separates local bit lines into different interconnect layers (first, second, third layers stacked in the vertical direction). This three-dimensional arrangement increases spatial separation between adjacent bit lines, reducing capacitive coupling noise while maintaining high memory capacity through increased word line stacking in the vertical direction.
Solution Approach 2:
By dividing the bit line signal path into multiple segmented local bit lines across different vertical layers, the patent isolates signal transmission paths. This segmentation reduces mutual interference and coupling noise between adjacent bit lines while enabling higher density through increased vertical stacking of memory structures.
Data Source
AI summary
According to one embodiment, a non-volatile semiconductor memory device includes a plurality of first interconnect layers stacked apart from each other, a memory pillar passing through the plurality of first interconnect layers, a local bit line electrically coupled to the memory pillar, a bit line, a plurality of second interconnect layers stacked apart from each other, a first pillar passing through the plurality of second interconnect layers and electrically coupled to the local bit line, a second pillar passing through the plurality of second interconnect layers and electrically coupled to the bit line and the first pillar, a plurality of third interconnect layers stacked apart from each other, and a third pillar passing through the plurality of third interconnect layers and electrically coupled to the bit line. At least one of the plurality of third interconnect layers is electrically coupled to the local bit line.