3D NAND Local Bit Line Structure for Faster High-Stack Reads
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Solution Overview
Problem
Current three-dimensional stacked NAND flash memory technologies face challenges in maintaining read operation speed and efficiency as the number of stacked word lines increases, leading to decreased cell current and prolonged read times due to high load capacitance and limited silicon mobility.
Innovation Solution
The implementation of a memory cell array structure with multiple interconnect layers and local bit lines, coupled with write and read port blocks, enhances the cell current and reduces load capacitance, allowing for increased word line stacking without compromising read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked word lines is increased to increase memory capacity, then memory capacity is improved, but read operation speed deteriorates due to prolonged read times
Solution Approach 1:
The bit line is divided into a first bit line and a second bit line that are electrically isolated from each other. Memory cell strings are selectively connected to different bit lines based on whether they contain odd or even numbers of turned-on memory cells. This segmentation allows independent read operations on different bit lines, preventing interference and maintaining read speed even as memory capacity increases through additional stacked word lines.
2Quantity of substance
If the number of stacked word lines is increased to increase memory capacity, then memory capacity is improved, but cell current decreases leading to prolonged read times
Solution Approach 1:
By dividing the bit line into electrically isolated first and second bit lines, the patent enables selective connection of memory cell strings based on the parity of turned-on cells. This segmentation reduces the total number of series-connected memory cells in each read path, thereby maintaining higher cell current levels even as the overall memory capacity increases through more stacked word lines.
Solution Approach 2:
The patent introduces a new dimension of organization by separating bit lines based on the parity (odd/even) of turned-on memory cells. This dimensional change in how bit lines are organized and connected allows the system to handle larger memory capacities while maintaining optimal read performance through parallel processing paths.
3Quantity of substance
If the number of stacked word lines is increased, then memory capacity is improved, but load capacitance increases causing read operation inefficiency
Solution Approach 1:
The bit line segmentation into first and second electrically isolated bit lines divides the total load capacitance into separate, manageable portions. Each bit line handles a subset of memory cell strings, reducing the capacitive burden on any single read path and improving overall read operation efficiency as memory capacity scales.
4Speed
If conventional approaches are used to maintain read speed, then read operation speed is maintained, but the number of word line layers is limited
Solution Approach 1:
The patent transitions from a conventional single bit line architecture to a multi-dimensional organization where bit lines are segmented and assigned based on the parity dimension of turned-on memory cells. This dimensional change enables the system to stack more word lines (increasing capacity) while maintaining read speed through the parallel, interference-free operation of segmented bit lines.
Data Source
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AI summary
According to one embodiment, a non-volatile semiconductor memory device includes a plurality of first interconnect layers stacked apart from each other, a memory pillar passing through the plurality of first interconnect layers, a local bit line electrically coupled to the memory pillar, a bit line, a plurality of second interconnect layers stacked apart from each other, a first pillar passing through the plurality of second interconnect layers and electrically coupled to the local bit line, a second pillar passing through the plurality of second interconnect layers and electrically coupled to the bit line and the first pillar, a plurality of third interconnect layers stacked apart from each other, and a third pillar passing through the plurality of third interconnect layers and electrically coupled to the bit line. At least one of the plurality of third interconnect layers is electrically coupled to the local bit line.