NAND Logic Page Generation for Flexible Multi-Bit Cell Modes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing NAND memory technologies face challenges in flexibly configuring multiple memory cell modes to balance fast write speed, high reliability, high storage capacity, and low cost, with current solutions being complex and costly.
Innovation Solution
A memory system utilizing hardware modules such as exclusive OR circuits, inverters, and access circuits in the controller to generate logic page data, allowing flexible configuration of NAND memory to support multiple cell modes, reusing existing components to reduce hardware costs and improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a storage system using NAND flash memory is designed to provide high-speed data processing, then data read/write speed is improved, but memory cells become vulnerable to disturbances from nearby charged memory cells, causing data errors
Solution Approach 1:
The patent introduces a shield electrode as an intermediary component positioned between adjacent memory cells. This shield electrode acts as a mediator that intercepts and redirects electric field disturbances from charged memory cells, preventing them from reaching and corrupting data in neighboring cells. The shield electrode is connected to a shield control circuit that monitors and adjusts the electric field environment, thereby protecting data integrity while maintaining the high-speed performance of the storage system.
Solution Approach 2:
The patent replaces physical isolation methods with an electric field-based protection mechanism. Instead of increasing physical distance or adding bulky shielding structures, the invention uses controlled electric fields generated by the shield control circuit to actively counteract disturbing fields. This substitution allows for compact design while maintaining both high-speed operation and data reliability through electronic field management rather than mechanical separation.
2Quantity of substance
If memory cells are positioned closer together to increase storage capacity, then storage density is improved, but the risk of data error from neighboring cell disturbances increases
Solution Approach 1:
The shield electrode serves as a protective intermediary inserted between closely positioned memory cells. It actively manages the electric field environment in the narrow spaces between cells, preventing charge leakage and data corruption. This allows the system to maintain high storage density with closely packed cells while the shield electrode continuously protects against inter-cell interference through dynamic field control.
Solution Approach 2:
The patent dynamically changes electric field parameters (voltage levels, field distribution) in response to detected disturbance conditions. The shield control circuit adjusts the electric field characteristics of the shield electrode based on real-time monitoring, modifying field strength and distribution to counteract specific interference patterns. This parameter adjustment allows closely spaced cells to operate reliably by adaptively managing the electric field environment between them.
3Productivity
If the storage system operates at high speed with frequent read/write operations, then productivity is improved, but the likelihood of data corruption from electric field disturbances increases
Solution Approach 1:
The shield control circuit operates continuously to maintain protective electric fields between memory cells during all read/write operations. Rather than activating shields only when errors are detected, the system maintains continuous field management throughout high-speed data processing. This continuous protection ensures that frequent write operations that generate electric field disturbances do not compromise data integrity in neighboring cells, enabling sustained high productivity without increased error rates.
Solution Approach 2:
The system implements a feedback mechanism where the shield control circuit monitors data integrity and electric field conditions in real-time during high-speed operations. When disturbances are detected that could lead to data corruption, the control circuit immediately adjusts shield electrode parameters to counteract the interference. This closed-loop feedback allows the system to maintain high productivity while dynamically correcting field disturbances that threaten data accuracy during intensive read/write operations.
Data Source
Figure 1(a)~2
Figure 3~4
Figure 5(a)~7
AI summary
Aspects of the disclosure are directed to a memory system that can include a controller and a memory coupled thereto, each memory cell of the memory is configured to store m-bit information, and the controller includes at least one of an exclusive OR circuit, an inverter and an access circuit. The controller is configured to receive n groups of logic page data, and generate, at different values of m and n, at least one group of logic page data selectively by at least one of the exclusive OR circuit, the inverter and the access circuit. The controller is further configured to transmit the m groups of logic page data to the memory to generate 2n different data states in the memory.