NAND Flash LUN Pairing for Bus Transmission Efficiency
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Solution Overview
Problem
The transmission efficiency of the NAND bus in Solid State Drives (SSDs) is inadequate, leading to suboptimal data writing performance, particularly in high-capacity SSDs with a large number of LUNs, resulting in idle waiting times and inefficient data transmission.
Innovation Solution
Pairing all logic units (LUNs) within each channel to form LUN pairs, allowing sequential and alternate data transmission within each pair, thereby utilizing short busy periods effectively and improving NAND bus transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple LUNs share the same NAND bus in a channel, then the device complexity is reduced, but the transmission efficiency of the NAND bus deteriorates
Solution Approach 1:
The patent segments the LUNs in each channel into pairs (LUN0-LUN1, LUN2-LUN3, etc.), allowing independent alternating transmission within each pair. This segmentation enables parallel processing of multiple LUNs while maintaining manageable complexity through systematic pairing and sequential operation.
2Device complexity
If multiple LUNs share the same NAND bus in a channel, then the device complexity is reduced, but the data writing performance deteriorates
Solution Approach 1:
The patent implements continuous useful action by alternating data transmission between paired LUNs during the short busy period (tPCBSY). While one LUN is being programmed, the other LUN in the pair can transmit data, ensuring the NAND bus remains continuously utilized without idle waiting time, thereby improving data writing performance.
3Ease of operation
If sequential writing is performed on each LUN without pairing, then the data transmission is simple, but idle waiting time increases
Solution Approach 1:
The patent applies periodic action by implementing an alternating transmission pattern between paired LUNs. The system periodically switches between LUNs in a pair, transmitting data to one LUN while the other is being programmed, and then switching back. This periodic alternation eliminates idle waiting time while maintaining operational simplicity through a regular, predictable pattern.
Data Source
AI summary
The present disclosure relates to a data writing method and apparatus of a NAND flash, and a storage medium. The method includes: for each channel in the NAND flash, pairing all logic units, namely LUNs, in the channel so that each LUN pair includes at least two LUNs; and for each LUN pair, sequentially writing data to one same page in a plurality of pages corresponding to a program mode included in each word line of each LUN in the LUN pair, and after completing data writing to the same page of the word line of all the LUNs in the LUN pair, sequentially writing data to a next same page in the plurality of pages of the word line of each LUN in the LUN pair, until the data writing is sequentially performed on a last same page in the plurality of pages of the word line of each LUN in the LUN pair. Therefore, the transmission efficiency of a NAND bus can be improved, and the data writing performance of the NAND flash can be improved.