NAND Memory Analytics Architecture for Data Processing Bottlenecks
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Solution Overview
Problem
Traditional data analytics systems face limitations in processing large datasets due to input/output constraints and power consumption, as they require transferring data from storage to computational modules for processing, which is inefficient and power-intensive.
Innovation Solution
Implementing a content addressable memory (CAM) system using NAND flash memory architecture that allows for on-chip data analytics by distributing analytic tasks across memory controllers and arrays, enabling parallel processing and reducing the need for data transfer, with keys stored along bit lines and searched simultaneously across all word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred from storage to computational modules for processing, then data analytics can be performed, but power consumption increases and processing speed decreases
Solution Approach 1:
The patent combines storage and computation functions into a single integrated system. NAND flash memory cells are configured to perform computational operations (such as comparisons, additions, and logical operations) directly within the memory array, eliminating the need to transfer data between separate storage and computational modules. This merging of functions reduces power consumption associated with data movement and accelerates processing by performing analytics operations in-place.
Solution Approach 2:
The memory system performs data analytics operations autonomously without requiring external computational resources. The control circuitry and memory arrays work together to execute analytic tasks internally, allowing the storage system to serve its own computational needs. This self-service capability eliminates dependency on separate processors and reduces the energy overhead of inter-module data transfer.
2Productivity
If data is transferred from storage to computational modules, then analytics operations can be executed, but input/output constraints limit processing efficiency
Solution Approach 1:
The patent merges storage and computation into an integrated architecture where NAND flash memory cells perform analytics operations directly. This eliminates the traditional separate I/O pathways between storage and computational modules, removing I/O constraints that limit processing efficiency. The unified system allows data to remain in place while being processed, bypassing bottlenecks associated with data transfer.
3Productivity
If conventional memory architecture is used, then data can be stored and retrieved, but parallel processing capability is limited
Solution Approach 1:
The patent segments the memory array into multiple independently controllable blocks or regions that can perform operations in parallel. Each segment can process different portions of data simultaneously, enabling mass parallel processing. This segmentation is achieved through careful organization of word lines and bit lines, allowing multiple comparison or computational operations to occur concurrently across different memory regions without requiring data to be moved to a centralized processor.
Data Source
AI summary
A data analytic system allows for analytic operations be moved from a server on to a solid state drive (SSD) type analytic system, where a CAM NAND structure can be used in the analytic operations. The server can run a software using database language can issue command to the analytic system. On the data analytic system (that can interface with common, existing database language), the software commands are translated into firmware language and broken down into multiple small tasks. The small tasks are executed on the SSD flash controllers or on NAND flash according to the task specifications. The mid-product from the NAND flash or the SSD controllers can be merged within each SSD blade and also further merged on the top server level.