NAND Memory Cell Layout Using Oxide Transistors and Back-Gate Readout
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Solution Overview
Problem
Current memory devices face challenges in achieving high reliability, large storage capacity, small area occupation, and low production costs, particularly in utilizing oxide semiconductors for transistors in memory cells.
Innovation Solution
A NAND memory device design incorporating multiple memory cells with writing and reading transistors, where oxide semiconductors are used in the semiconductor layers, eliminating the need for a storage capacitor or reducing its size, and utilizing a back gate in reading transistors to facilitate data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a storage capacitor is used in each memory cell, then data can be stored, but the area occupied by each memory cell increases
Solution Approach 1:
The patent extracts the storage capacitor from the traditional memory cell structure by utilizing the gate electrode and gate insulating layer of the transistor itself to form a capacitor structure. This eliminates the need for a separate storage capacitor, thereby reducing the memory cell area while maintaining data storage capability.
Solution Approach 2:
The gate electrode and gate insulating layer serve dual functions: they act as both the control elements of the transistor and the storage elements of the capacitor. This multi-functionality reduces the number of separate components needed in each memory cell, decreasing overall area occupation.
2Reliability
If oxide semiconductors are used in transistors, then off-state current is reduced and reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes the unique electrical parameters of oxide semiconductor materials, particularly their extremely low off-state current characteristics, to achieve high-reliability memory operation. By leveraging these inherent material properties rather than attempting to modify them, the approach simplifies the overall manufacturing process despite using advanced materials.
3Area of moving object
If the gate insulating layer is made thin to reduce area, then area is reduced but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different thickness requirements to different regions of the gate insulating layer based on their specific functions. The insulating layer serving as the capacitor dielectric can be optimized for capacitance density, while other regions maintain sufficient thickness for electrical isolation, thereby reducing overall area without excessively increasing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a highly reliable memory device with increased storage capacity, reduced area occupation, and lower production costs, while maintaining high reliability and endurance even in high-temperature environments.
Implementation Method 1
An OS transistor has an extremely low off-state current (a current flowing between the source and the drain when the transistor is in an off-state)
Implementation Method 2
The reading transistor includes a back gate. When a reading voltage is applied to the back gate, data stored in the memory cell can be read.
Data Source
AI summary
A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory cells each provided with a writing transistor, a reading transistor, and a capacitor. An oxide semiconductor is used in a semiconductor layer of the writing transistor. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, information stored in the memory cell is read out.