NAND Memory Programming to Cut Two-Step Buffer Capacity
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Solution Overview
Problem
Semiconductor storage devices like NAND flash memories require significant resources for temporarily storing data during two-step program operations, leading to increased capacity demands due to power loss protection, necessitating techniques to reduce the amount of data stored.
Innovation Solution
A memory system with a nonvolatile memory and a memory controller that performs two-step program operations of different types to write multi-bit data, reducing the amount of data required to be stored by setting threshold voltages in specific voltage ranges during these operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two-step program operations are executed with power loss protection, then data reliability is improved, but memory capacity requirements increase
Solution Approach 1:
The patent segments the program operation into two distinct steps: a first program operation that writes data to memory cells, and a second program operation that verifies and completes the writing. This segmentation allows the controller to manage data in smaller chunks, reducing the amount of data that must be held in buffer memory at any one time while maintaining reliability through the verification step.
Solution Approach 2:
The patent performs preliminary actions by executing the first program operation to write data to memory cells before completing the full write cycle. During this preliminary phase, data is written to the memory cells themselves rather than being held entirely in buffer memory, reducing buffer requirements. The second program operation then completes the write cycle with verification, ensuring reliability without requiring all data to remain in buffer throughout the entire process.
2Reliability
If data is temporarily stored in buffer memory during two-step program operations, then power loss protection is enabled, but resource requirements increase
Solution Approach 1:
The patent dynamically adjusts the amount of data held in buffer memory during the two-step program operation. In the first program operation, only the portion of data needed for the current memory cell being programmed is held in buffer, rather than holding all data. The buffer is then cleared or reused for the next operation. This dynamic management reduces the peak buffer memory requirements while maintaining the ability to perform power loss protection for the data currently being processed.
3Quantity of substance
If larger buffer memory is allocated for two-step operations, then data storage capability is improved, but system cost increases
Solution Approach 1:
The patent changes the operational parameters of the buffer memory by utilizing it in a time-multiplexed manner. Instead of allocating buffer memory to hold all data simultaneously, the system reuses the same buffer memory for different data portions across the two program operations. The buffer size parameter is optimized to hold only the minimum necessary data for each operation step, reducing the overall buffer capacity requirement and thus lowering system cost while maintaining adequate data storage capability for each operational phase.
Data Source
AI summary
A memory system includes a nonvolatile memory including first, second, and third arrays of memory cells and a memory controller. The memory controller is configured to perform a two-step program operation of a first type on the first and second arrays. The first type includes a first program operation to set a threshold voltage of the memory cell to be in one of a first plurality of ranges, and then a second program operation to set the threshold voltage to be in one of a second plurality of ranges. The memory controller is configured to perform a two-step program operation of a second type on the third array. The second type includes a third program operation to set a threshold voltage corresponding to partial bits of the multi-bit data, and then a fourth program operation to set a threshold voltage corresponding to the entire bits of the multi-bit data.