NAND Memory Charge Trapping Segmentation
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Solution Overview
Problem
Conventional NAND memory architectures face data retention issues due to charge migration between memory cells caused by charge-trapping material extending across multiple cells, leading to inaccurate data storage.
Innovation Solution
Incorporating breaks in the charge-trapping material between memory cells and using a vertical stack configuration with conductive levels, charge-blocking material, and channel material to impede charge migration, while optimizing the thickness and configuration of charge-storage and gate-dielectric materials for improved data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge-trapping material is used to store charge in NAND memory cells, then data storage capability is improved, but charge migration between adjacent memory cells occurs causing data retention issues
Solution Approach 1:
The charge-blocking material is divided into multiple segments positioned at different vertical levels between adjacent memory cell strings. These segments create isolated barrier regions that prevent charge migration while maintaining charge storage capability in the charge-trapping material. The segmentation approach allows the system to retain sufficient charge for data storage while blocking unwanted charge migration paths.
Solution Approach 2:
The charge-blocking material acts as an intermediary element positioned between adjacent memory cell strings. This intermediary material specifically blocks charge migration between cells while allowing the charge-trapping material to perform its data storage function. The charge-blocking segments serve as mediating structures that resolve the conflict between charge storage and charge isolation requirements.
2Reliability
If charge-blocking material segments are added to prevent charge migration, then data retention accuracy is improved, but device structural complexity increases
Solution Approach 1:
The charge-blocking material segments are integrated into the existing vertical stack architecture of the NAND memory device. Rather than adding completely separate structures, the charge-blocking segments are combined with the charge-trapping material and gate structures in a unified vertical arrangement. This merging approach reduces the overall structural complexity compared to implementing charge blocking through separate external mechanisms.
Solution Approach 2:
The charge-blocking functionality is implemented by utilizing the vertical dimension of the memory structure. Instead of adding lateral or planar complexity to block charge migration, the solution uses vertically-stacked charge-blocking segments at different height levels. This dimensional approach allows charge blocking without significantly increasing overall device complexity, as the vertical stack is already inherent to the 3D NAND architecture.
3Ease of manufacture
If conventional NAND memory architecture is used with continuous charge-trapping material, then manufacturing process simplicity is maintained, but charge migration causes data retention problems
Solution Approach 1:
The charge-blocking material is segmented into multiple discrete portions positioned at different vertical levels. This segmentation can be achieved through standard semiconductor fabrication techniques such as selective deposition and etching processes. The segmented structure maintains compatibility with conventional manufacturing workflows while providing the necessary charge isolation functionality that continuous material structures cannot provide.
Data Source
AI summary
Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have primary regions of a first vertical thickness, and have terminal projections of a second vertical thickness which is greater than the first vertical thickness. The terminal projections include control gate regions. Charge-blocking regions are adjacent the control gate regions, and are vertically spaced from one another. Charge-storage regions are adjacent the charge-blocking regions and are vertically spaced from one another. Gate-dielectric material is adjacent the charge-storage regions. Channel material is adjacent the gate dielectric material. Some embodiments included methods of forming integrated assemblies.