3D NAND Memory Chip Layout for Faster On-Chip Data Transfer
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Solution Overview
Problem
Existing NAND flash memory devices face challenges in integrating high-density three-dimensional memory structures with CMOS circuits on separate chips, leading to inefficiencies in data storage and retrieval.
Innovation Solution
A memory device configuration that integrates a memory cell array with a CMOS circuit on a single chip, utilizing a first chip with a memory cell array and a second chip with a substrate and circuit, connected through input/output pads, and employing high breakdown voltage transistors for efficient data transfer and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND flash memory uses separate chips for three-dimensional memory structure and CMOS circuit, then high integration and large capacity are achieved, but bonding complexity and device reliability deteriorate
Solution Approach 1:
The patent merges the memory cell array and CMOS circuit onto a single chip, eliminating the need for bonding between separate memory chip and circuit chip. This integration approach maintains high capacity while reducing bonding complexity and improving reliability by removing the inter-chip interface.
2Ease of manufacture
If NAND flash memory uses separate chips for memory and circuit, then manufacturing flexibility is improved, but data transfer speed and retrieval efficiency deteriorate
Solution Approach 1:
By integrating the CMOS circuit directly with the memory cell array on the same chip, the patent eliminates data transfer delays between separate chips. The unified architecture enables direct access between circuit and memory, significantly improving data transfer speed and retrieval efficiency while maintaining manufacturing feasibility through single-chip fabrication processes.
Data Source
AI summary
A memory device includes: a first chip including a memory cell array having a word line and a bit line; a second chip including a first substrate and a first circuit provided on the first substrate, the second chip being in contact with the first chip; a third chip including a second substrate and a second circuit provided on the second substrate, the third chip being in contact with the first chip or the second chip; and an input/output pad. The first chip and the second chip are arranged in this order in a first direction from the word line to the bit line. The first circuit includes a first transistor connected to the bit line and a second transistor connected to the word line. The second circuit includes a third transistor connected to the input/output pad.