NAND Memory Command Queuing for Parallel Processing
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Solution Overview
Problem
Existing memory systems with multiple NAND flash memory chips face inefficiencies in processing concurrent commands, leading to elongated processing times due to sequential execution and idle states of memory chips, especially in multitask systems where requests are processed sequentially rather than in parallel.
Innovation Solution
The implementation of priority command queues within the NAND interface allows for prioritizing commands accessing idle NAND memory chips, enabling concurrent execution and improving overall transfer performance by executing commands from priority queues before completing ordinary command queue tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If commands are processed sequentially in a single queue, then the system is simple to manage, but the processing time is elongated and memory chips remain in idle states
Solution Approach 1:
The patent divides a single command queue into multiple command queues (first command queue and second command queue). This segmentation allows the system to process commands from different queues in parallel, reducing idle time for memory chips while maintaining manageable complexity through organized queue structures.
Solution Approach 2:
The patent introduces a new dimension to command processing by implementing multiple command queues that can be processed in different execution orders. The first command queue processes commands in reception order, while the second command queue processes commands in reverse order, enabling parallel processing paths that reduce overall processing time without significantly increasing system complexity.
2Adaptability or versatility
If multiple commands are queued for the same memory chip, then command buffering is improved, but processing efficiency decreases due to sequential execution
Solution Approach 1:
The patent segments commands destined for the same memory chip into different command queues based on their processing priority and timing. By distributing commands across multiple queues with different execution strategies (normal order vs. reverse order), the system maintains buffering capability while improving processing efficiency through parallel execution paths.
Solution Approach 2:
The patent implements dynamic command processing by allowing the system to switch between processing commands in normal reception order (first command queue) and reverse order (second command queue). This dynamic approach enables the system to optimize processing efficiency based on command characteristics and memory chip availability, transforming static sequential execution into adaptive parallel processing.
3Ease of operation
If the system processes commands in reception order only, then command execution is simple, but memory chips experience idle states reducing throughput
Solution Approach 1:
The patent segments command execution into two distinct pathways: the first command queue processes commands in simple reception order, while the second command queue processes commands in reverse order. This segmentation allows the system to maintain operational simplicity for time-critical commands while improving throughput through reverse-order processing of other commands, reducing memory chip idle states.
Solution Approach 2:
The patent adds a reverse-order processing dimension to the traditional first-in-first-out command execution model. By implementing a second command queue that processes commands in reverse reception order, the system expands the operational space from single-dimension sequential processing to multi-dimension parallel processing, improving throughput while maintaining ease of operation through clear queue management rules.
Data Source
AI summary
According to one embodiment, there is provided a memory system including a nonvolatile semiconductor memory, a bus, and a controller. The nonvolatile semiconductor memory includes a first chip and a second chip. The bus is connected to the first chip and the second chip in common. The controller issues a first command to the first chip via the bus. The controller queues a second command whose access destination is identified to be the first chip at a first timing while the first chip is executing the first command. The controller issues to the second chip a third command whose access destination is identified to be the second chip after the first timing, via the bus in priority over the second command, while the first chip is executing the first command or after the execution of the first command finishes.