NAND Memory Post-Read Disturb Reduction via Voltage Control
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Solution Overview
Problem
Memory devices, particularly non-volatile semiconductor memory, face challenges in reducing post-read disturbance that can lead to increased bit error rates due to floating word line voltages and temperature-related issues, affecting data integrity and storage reliability.
Innovation Solution
Implementing techniques to manage word line voltages by discharging them to zero volts or maintaining a low positive voltage after a read operation, and optimizing control gate and select gate voltage pulses to minimize channel coupling and residual potential, thereby reducing disturb effects and maintaining data accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If word line voltages are allowed to float after a read operation, then device complexity is reduced, but post-read disturbance increases leading to higher bit error rates
Solution Approach 1:
The patent applies preliminary action by discharging word line voltages to zero volts or maintaining them at a low positive voltage immediately after a read operation, before disturbance can occur. This proactive voltage management prevents post-read disturbance and bit errors rather than correcting them later, resolving the contradiction between simplified voltage management and data integrity.
2Measurement precision
If voltage pulses are increased to improve read sensing, then measurement precision is improved, but channel coupling and residual potential increase causing more disturbance
Solution Approach 1:
The patent applies preliminary anti-action by optimizing control gate and select gate voltage pulses to minimize channel coupling and residual potential during the read operation. By carefully controlling the voltage pulse parameters, the patent prevents excessive channel coupling that would lead to post-read disturbance, thus counteracting the harmful effect while maintaining adequate read sensing precision.
Solution Approach 2:
The patent applies parameter changes by adjusting the amplitude, duration, and timing of control gate and select gate voltage pulses to optimize the read operation. By changing these voltage parameters, the patent achieves sufficient sensing precision while minimizing residual channel coupling and subsequent disturbance, resolving the contradiction between measurement precision and harmful coupling effects.
3Productivity
If read operation speed is increased, then productivity is improved, but voltage discharge time is reduced leading to increased disturbance
Solution Approach 1:
The patent applies preliminary action by implementing fast voltage discharge mechanisms that quickly reduce word line voltages to zero or low positive voltage immediately after the read operation. This rapid voltage management occurs within the shortened time window created by high-speed operations, preventing disturbance before it can affect stored data, thus resolving the contradiction between read speed and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces post-read disturbance, lowers bit error rates, and maintains data integrity by controlling word line voltages and optimizing voltage pulses, enhancing the reliability of memory devices.
Implementation Method 1
optimizing control gate and select gate voltage pulses to minimize channel coupling and residual potential
Data Source
AI summary
An apparatus includes a plurality of NAND strings in a block with word lines connected to cells of the NAND strings and select lines connected to select gate transistors of the NAND strings. A control circuit is configured to, after a read operation of memory cells of the block apply substantially zero volts to the global word lines to discharge the word lines to substantially zero volts. The control circuit is further configured to turn off the select gate transistors to isolate channels, turn off the block select transistors to isolate the word lines from the global word lines, and with the block select transistors turned off, apply a low positive voltage on the global word lines.