NAND Memory Dual-Block Write Control for Faster Programming
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in improving the speed of write operations, particularly in NAND flash memory systems.
Innovation Solution
The semiconductor memory device employs a dual-block structure with separate control circuits for each block, allowing simultaneous write operations to be performed in one block while maintaining a floating state in another, thereby enhancing write speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sequential write operations are performed in single-block structure, then device complexity is reduced, but write operation speed deteriorates
Solution Approach 1:
The memory device is divided into multiple independent blocks (first block and second block), each capable of performing write operations independently. This segmentation allows parallel execution of write operations across different blocks, thereby improving write speed without requiring complex inter-block coordination mechanisms.
Solution Approach 2:
The patent transitions from a single-block sequential write architecture to a multi-block parallel write architecture, adding a spatial dimension (block dimension) to the write operation capability. This dimensional expansion enables simultaneous write operations in different blocks, improving overall write throughput.
2Productivity
If parallel write operations are implemented in dual-block structure, then write operation speed is improved, but device complexity increases
Solution Approach 1:
The control functionality is segmented into independent control circuits for each block. Each control circuit manages write operations for its associated block autonomously, eliminating the need for a complex centralized control mechanism and reducing overall system complexity while maintaining parallel productivity.
Solution Approach 2:
Each block is designed with identical functional capabilities and independent control circuits, allowing any block to perform any write operation independently. This universal design simplifies the control architecture by using replicated, standardized units rather than complex specialized control logic.
3Speed
If floating state is maintained in one block during write, then write speed is improved, but operation reliability may deteriorate
Solution Approach 1:
Data is segmented across multiple independent blocks, each with its own control circuit. The floating state operation in one block does not affect the integrity of data in other blocks, as each block operates independently with isolated control mechanisms, maintaining overall system reliability.
Solution Approach 2:
Independent control circuits act as intermediaries between the write operation commands and the memory blocks. These control circuits manage the floating state transitions and ensure proper data integrity protocols are followed in each block, preventing reliability deterioration while enabling speed improvements.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a first block and a second block, and a control circuit. The control circuit executes a first write operation of writing first data by applying a first voltage to a channel area of a first memory cell transistor of the first block through a bit line and then while the channel area of the first memory cell transistor is in a floating state, applying a program voltage to a first word line. The control circuit starts a second write operation of writing second data into a second memory cell transistor of the second block that is connected to the bit line while the program voltage is applied to the first word line.