Dual-Transistor NAND Memory Cell for Faster Program and Erase
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Solution Overview
Problem
Existing NAND flash memory technologies suffer from low programming and erase operation speeds due to low F-N tunneling and thermal currents, limiting their efficiency and density.
Innovation Solution
A memory cell design featuring transistors with separated gates and specific electrode connections, enabling high-speed and high-density memory operations through improved writing and reading methods, including a three-dimensional stacked structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a basic NAND flash block adopts a series connection structure without contact, then memory density is improved and area is reduced, but programming and erase operation speeds are limited due to low F-N tunneling and thermal currents
Solution Approach 1:
The patent divides the memory cell into two separate transistors (first transistor and second transistor) with separated gates, allowing independent control of each transistor. This segmentation enables the first transistor to handle programming operations while the second transistor handles reading operations, thereby improving operational speed without compromising the space-saving series connection structure
Solution Approach 2:
The patent introduces a three-dimensional stacked structure with multiple memory cells connected in series vertically, transitioning from a planar arrangement to a vertical stacking arrangement. This dimensional change increases memory density by utilizing the vertical space while maintaining the low F-N tunneling current characteristics through optimized gate and electrode connections
2Quantity of substance
If a three-dimensional stacked structure is used, then memory density is further improved, but device complexity increases
Solution Approach 1:
The patent designs the first transistor and second transistor with shared electrodes and gates that serve multiple functions. The first electrode of the first transistor serves as the second electrode of the second transistor, and both transistors share common word line connections. This multi-functionality reduces the overall number of separate components needed in the three-dimensional stacked structure, thereby reducing device complexity while maintaining high memory density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances memory cell array performance with faster writing and refreshing speeds, and increased density by optimizing transistor connections and voltage application during read and write operations.
Implementation Method 1
charges can be injected into or ejected from the floating gate by F-N tunneling or thermal injection
Implementation Method 2
charges can be injected into or ejected from the floating gate by F-N tunneling or thermal injection
Data Source
AI summary
A memory cell, an NAND string, a memory cell array, and a data access method. The memory cell comprises a first transistor and a second transistor, the first transistor comprises a first electrode, a second electrode, and two independent gates, i.e., a first gate and a second gate; the second transistor comprises a first electrode, a second electrode, and a gate; the first gate of the first transistor is used as a first word line connecting end; the gate of the second transistor is used as a second word line connecting end; and the second gate of the first transistor is connected to the first electrode of the second transistor.