3D NAND Memory Program Control with Dynamic Pre-Pulse
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
3D NAND memory devices experience hot carrier injection (HCI) due to channel potential differences between select and unselect memory strings during program/verify cycles, which disturbs programming, and the additional pre-pulse stage to address this issue increases program time.
Innovation Solution
A solution that dynamically adds or omits the pre-pulse stage based on the comparison between the initial verify voltage and a threshold verify voltage, reducing HCI while optimizing program time by turning on the DSG transistor in unselect memory strings only when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a pre-pulse stage is added to address hot carrier injection, then HCI interference is reduced, but program time increases
Solution Approach 1:
The patent applies dynamics by making the pre-pulse stage optional rather than mandatory. The control circuit dynamically determines whether to apply the pre-pulse stage based on real-time comparison between the initial verify voltage and a threshold verify voltage. When the initial verify voltage is lower than the threshold, the pre-pulse stage is applied to reduce HCI; when the initial verify voltage is higher, the pre-pulse stage is omitted to save time. This dynamic adjustment resolves the contradiction between reducing HCI interference and minimizing program time.
Solution Approach 2:
The patent changes the parameter of verify voltage threshold comparison to control the pre-pulse stage application. By comparing the initial verify voltage with a threshold verify voltage and adjusting the pre-pulse stage accordingly, the system optimizes the balance between HCI reduction and programming speed. This parameter-based control allows the system to adapt to different programming conditions and achieve optimal performance.
2Manufacturing precision
If the pre-pulse stage is applied to reduce HCI, then programming accuracy is improved, but productivity decreases
Solution Approach 1:
The system dynamically adjusts the pre-pulse stage application based on voltage comparison results. When the initial verify voltage indicates potential HCI issues (lower than threshold), the pre-pulse stage is applied to ensure programming accuracy. When the voltage indicates HCI is not an issue (higher than threshold), the pre-pulse stage is omitted to maintain high productivity. This dynamic approach ensures programming accuracy is maintained only when necessary, preserving overall productivity.
Solution Approach 2:
The patent uses parameter changes in the verify voltage threshold comparison to control when the pre-pulse stage is applied. By adjusting the threshold verify voltage and comparing it with the initial verify voltage, the system determines the optimal timing for pre-pulse application. This parameter-based control ensures programming accuracy is improved when HCI is detected, while maintaining high programming speed when HCI is not present.
3Object-affected harmful factors
If the DSG transistor is turned on in unselect memory strings, then channel potential difference is reduced, but device complexity increases
Solution Approach 1:
The patent applies local quality by selectively controlling the DSG transistor in unselect memory strings based on local conditions. Instead of uniformly applying the pre-pulse stage to all memory strings, the control circuit compares the initial verify voltage with the threshold verify voltage and only activates the pre-pulse stage (turning on DSG transistors) when the voltage comparison indicates HCI risk. This localized, conditional control reduces channel potential difference only where necessary, avoiding unnecessary complexity in the control system.
Data Source
AI summary
A memory device includes a memory array including memory strings and a first word line, and a peripheral circuit coupled to the memory array. Each memory string includes a select gate transistor and memory cells. The peripheral circuit is configured to apply, during a first time period, a program voltage to the first word line to program a first memory cell in a selected memory string, apply, during a second time period after the first time period, a first verify voltage to the first word line to verify the first memory cell, compare the first verify voltage with a target voltage to obtain a comparing result, and in response to the comparing result indicative of the first verify voltage being higher than the target voltage, turn off, during a third time period between the first and the second time periods, the select gate transistor in an unselected memory string.