3D NAND Memory Reading Disturbance via Electric Field Reversal
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Solution Overview
Problem
Three-dimensional NAND flash memory devices face reading disturbances due to electron trapping in the gate insulating film during the reading operation, which affects data reliability and requires high correction capability ECC circuits, increasing chip costs.
Innovation Solution
The memory device applies a read voltage to the selected word line and a read pass voltage to unselected word lines, then reverses the electric field to move trapped electrons back to the semiconductor pillar, preventing reading disturbances without the need for high correction capability ECC circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a read pass voltage is applied to unselected word lines during reading operation, then reading speed is improved, but electron trapping in the gate insulating film occurs causing reading disturbance
Solution Approach 1:
The patent applies a recovery voltage with reverse polarity to the unselected word line after the read pass voltage is applied. This inverts the electric field direction to extract trapped electrons from the gate insulating film, thereby eliminating reading disturbance while maintaining the speed benefits of the read pass voltage approach
2Reliability
If high correction capability ECC circuits are used to correct reading disturbances, then data reliability is improved, but chip cost increases
Solution Approach 1:
The patent applies a recovery voltage with reverse polarity to the unselected word line immediately after the read pass voltage, before reading disturbances can significantly affect data reliability. This preventive approach eliminates the need for complex ECC circuits by cushioning against reading disturbances in advance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data reading reliability and reduces chip costs by eliminating the need for advanced ECC circuits, while maintaining data integrity and reducing reading disturbance.
Implementation Method 1
reading disturbances due to electron trapping in the gate insulating film during the reading operation
Implementation Method 2
reverses the electric field to move trapped electrons back to the semiconductor pillar
Data Source
AI summary
A memory device includes a semiconductor pillar, a first memory cell that includes a first memory film between a first word line and a side surface of the semiconductor pillar, a second memory cell that includes a second memory film between a second word line and the side surface of the semiconductor pillar, and a control circuit configured to carry out first and second operations on the first memory cell and the second memory cell during a reading operation. During the first operation, a read voltage is applied to the first word line and a read pass voltage is applied to the second word line, and during the second operation following the first operation, a first voltage is applied to the second word line, such that a potential of the second word line is lower than a potential of the semiconductor pillar.