NAND Memory Intermediate Buffers for Concurrent Sequential Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile memories like NAND flash face challenges in accelerating processing times due to thrashing of sense results when receiving concurrent sequential read commands, which necessitate repeated sensing operations and hinder efficient data transfer.
Innovation Solution
Implementing a nonvolatile memory system with multiple intermediate buffers and a control circuit that allocates these buffers to specific threads, allowing explicit designation of storage destinations and inter-latch data transfers, thereby reducing unnecessary sensing operations and enhancing data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single input/output buffer is used for data transfer, then the memory structure is simple, but concurrent sequential read commands cause thrashing and require repeated sensing operations
Solution Approach 1:
The patent divides the single input/output buffer into multiple intermediate buffers (first intermediate buffer, second intermediate buffer, etc.) that are respectively allocated to different threads. This segmentation allows concurrent sequential read commands from different threads to be processed in parallel without thrashing, as each thread has its own dedicated intermediate buffer for storing sense results. The control circuit routes data from the memory cell array to the appropriate intermediate buffer based on thread identification, eliminating the need for repeated sensing operations.
Solution Approach 2:
The intermediate buffers serve as intermediary structures between the memory cell array and the input/output buffer. Instead of directly transferring data from the memory cell array to the input/output buffer for concurrent reads, the system uses intermediate buffers as mediators to temporarily store sense results for different threads. This intermediary layer enables efficient data transfer by allowing multiple threads to access their respective buffers simultaneously without interfering with each other.
2Loss of time
If repeated sensing operations are performed for concurrent read commands, then data can be transferred, but processing time increases
Solution Approach 1:
The control circuit performs preliminary identification of threads receiving concurrent sequential read commands and pre-allocates appropriate intermediate buffers for each thread before data transfer begins. By determining thread assignments in advance and routing sense results to the correct intermediate buffers upfront, the system avoids the need for repeated sensing operations and reduces processing time while maintaining high data transfer throughput.
Data Source
AI summary
According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.