NAND Memory Array Self-Test via Programmable Macro Execution
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Solution Overview
Problem
Current memory devices require time-consuming and costly processes for testing and updating instructions and commands, especially during the development and production phases, due to the need for metal mask changes and the inefficiency of using SRAM for storing test instructions, which consumes valuable real estate and resources.
Innovation Solution
Implementing a memory device that allows for immediate implementation of test instructions and commands without metal mask changes, by storing macro and operation code data in a memory array, enabling self-test operations and reducing the need for SRAM, allowing for flexible storage and execution of macros and commands directly from the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional memory circuitry is used to store test instructions and commands, then test operations can be performed, but real estate on the device is consumed and the circuitry must be removed for production versions
Solution Approach 1:
The memory array is designed to serve dual purposes: storing user data during normal operation and storing test instructions/commands during testing phases. The control circuitry enables the memory array to be reconfigured or accessed in different modes, allowing the same physical space to fulfill multiple functions without requiring separate dedicated test memory circuitry.
Solution Approach 2:
The memory device performs self-test operations by executing test instructions and commands that are stored within its own memory array. The control circuitry enables the device to autonomously conduct testing without requiring external testing equipment or separate test memory, thereby eliminating the need for additional memory circuitry while maintaining test capability.
2Reliability
If hard coded test instructions and commands are used, then test operations can be stored, but changing or updating them is time consuming and labor intensive
Solution Approach 1:
The system transitions from static hard-coded test instructions to dynamic, programmable test instructions stored in the memory array. The control circuitry allows test instructions to be loaded, updated, and modified through standard memory programming interfaces, enabling rapid changes without requiring physical reconfiguration or labor-intensive processes.
Solution Approach 2:
The test instructions are stored as programmable data in the memory array rather than being hard-coded into fixed circuitry. This allows the content of test instructions to be changed by simply rewriting the memory cells, transforming the system from a fixed parameter state to a flexible, reconfigurable state that can be updated quickly and easily.
3Reliability
If manual probing devices are used for device testing, then verification can be performed, but the process is tedious and time consuming
Solution Approach 1:
The memory device performs self-test operations by executing test instructions and commands stored in its own memory array. The control circuitry enables autonomous testing where the device tests itself without requiring external manual probing or intervention, thereby eliminating the tedious manual process while maintaining comprehensive verification capability.
Solution Approach 2:
The patent replaces the mechanical manual probing process with an automated electronic self-test system. Instead of physical probes and manual operations, the device uses electronic memory storage and control circuitry to automatically execute test sequences, substituting mechanical operations with electronic automation to improve productivity.
4Reliability
If SRAM is used to store test instructions, then test operations can be performed, but valuable real estate is consumed
Solution Approach 1:
The memory array is designed to serve dual purposes: storing user data during normal operation and storing test instructions/commands during testing phases. By making the memory array universal rather than dedicating separate SRAM for testing, the system eliminates the need for additional memory resources while maintaining both data storage and test instruction storage capabilities.
Solution Approach 2:
The memory device uses its own primary memory array to store and execute test instructions, eliminating the need for separate SRAM resources. The control circuitry enables the memory array to be accessed in different modes, allowing the device to self-test using its existing memory resources rather than requiring additional dedicated test memory.
Data Source
AI summary
Methods of performing an internal diagnostic for a NAND configured memory device include storing data in a data cache coupled to an array of memory cells arranged in a NAND configuration, wherein the data stored in the data cache corresponds to at least one diagnostic function; performing a decode operation on the data stored in the data cache, wherein the decode operation generates a diagnostic function command for testing internal functions of the NAND configured memory device; and providing the decoded diagnostic function command to a state machine of the NAND configured memory device adapted to perform the decoded diagnostic function command.