NAND Memory Device with Metal Oxide Transistors for Low Power
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Solution Overview
Problem
Current data processing devices face challenges in reducing power consumption, particularly due to increased leakage currents in scaled-down transistors, which lead to higher circuit area and power consumption, and the need for separate bus lines between cache and NAND memory devices, increasing circuit area and power usage.
Innovation Solution
A data processing device incorporating NAND memory portions with strings of transistors using metal oxides in the channel formation region, where a controller manages data transfer between memory cells across different strings, optimizing data writing, reading, and deletion operations to reduce power consumption and circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are scaled down to increase integration, then device density is improved, but leakage current increases leading to higher power consumption
Solution Approach 1:
The patent combines the cache memory and NAND memory device into a single integrated device, eliminating the need for separate bus lines and reducing overall power consumption. The cache memory uses metal oxide transistors with extremely low off-state current to retain data without continuous power supply, merging the functions of temporary storage and non-volatile storage in one device structure.
Solution Approach 2:
The patent changes the material parameter of the transistor from conventional semiconductor to metal oxide semiconductor, which fundamentally alters the off-state current characteristics. This parameter change enables the transistor to maintain an extremely low off-state current even when scaled down, allowing high device density without the usual increase in leakage current and power consumption.
2Ease of operation
If separate bus lines are used between cache and NAND memory devices, then data transfer is simplified, but circuit area and power consumption increase
Solution Approach 1:
The patent merges the cache memory and NAND memory device into a single integrated structure where data transfer occurs internally without requiring external bus lines. The controller directly manages data movement between the cache memory portion and NAND memory portion within the same device, eliminating the need for separate connection pathways and reducing overall circuit area.
Solution Approach 2:
The patent extracts the bus line requirement from the system by integrating the cache and NAND memory functions into one device. The data transfer function is retained but the physical bus lines connecting separate devices are eliminated, as the two memory portions now share a common substrate and control structure.
3Ease of operation
If separate bus lines are used between cache and NAND memory devices, then data transfer is simplified, but power consumption increases
Solution Approach 1:
The patent combines the cache memory and NAND memory device into a single integrated device, eliminating the need for separate bus lines and reducing overall power consumption. The cache memory uses metal oxide transistors with extremely low off-state current to retain data without continuous power supply, merging the functions of temporary storage and non-volatile storage in one device structure.
4Use of energy by moving object
If power gating is implemented in CPU to reduce standby power, then static power consumption is reduced, but break-even time increases affecting normal operation
Solution Approach 1:
The patent changes the transistor material to metal oxide semiconductor, which has fundamentally different electrical characteristics including an extremely low off-state current. This parameter change enables the transistor to maintain data without power supply, achieving true standby power elimination without the time penalty associated with conventional power gating implementations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a data processing device with reduced circuit area and low power consumption by efficiently managing data operations across memory strings with metal oxide transistors, thereby addressing the limitations of existing technologies.
Implementation Method 1
A memory circuit capable of retaining data even when power is off, which takes advantage of a feature of an extremely low off-state current of a transistor including an oxide semiconductor (also referred to as Oxide Semiconductor or simply OS) in its channel formation region
Data Source
AI summary
A data device with a small circuit area and reduced power consumption is used. The data processing device includes a NAND memory portion and a controller. The memory portion includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell.