Monotonic NAND Memory Counters With Power-Loss Tolerant Writes
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Solution Overview
Problem
Memory systems, particularly non-volatile storage memories like NAND flash, are susceptible to data degradation and bit error rates, which can lead to issues such as replay attacks due to the need for frequent writing and the inability to use error correction codes for counting operations.
Innovation Solution
Implementing a monotonic counter system with a volatile counter and a non-volatile memory array, where information is written only after a certain number of increments, using redundant bits to compensate for high bit error rates and incorporating a mechanism to ensure a monotonically increasing count even after power loss, by initializing the count based on previous writes and swapping storage blocks to maintain a large counting range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If information is written to the memory array each time the counter is incremented, then the count is accurately recorded, but the memory array degrades faster due to excessive write operations
Solution Approach 1:
The patent applies partial action by writing to the memory array only when the counter reaches a threshold value (e.g., every 2^16 increments) rather than after every single increment. This reduces the number of write operations from potentially millions to just a handful, significantly extending memory array lifespan while still maintaining sufficient count recording capability through the combination of volatile and non-volatile storage
2Ease of operation
If the volatile counter is initialized to zero after power loss, then the counting starts fresh, but the count may decrease which enables replay attacks
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing an initialization value in the memory array before power loss occurs. When power is restored, this stored value is retrieved and used to initialize the volatile counter, ensuring it resumes from a valid previous state rather than zero. This preliminary preparation prevents count decrease and maintains monotonicity, thereby preventing replay attacks
3Reliability
If redundant bits are added to compensate for bit error rates, then the reliability against errors improves, but the device complexity increases
Solution Approach 1:
The patent uses the memory array as an intermediary storage structure that holds both the counter value and redundant check bits. Rather than implementing complex error correction circuits directly in the counter logic, the system leverages the memory array's inherent structure and simple read/write operations to store and verify redundant information, achieving error resistance with minimal additional complexity
Data Source
AI summary
An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.