NAND Memory Page-State Generation for Flexible SLC to QLC Modes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND memory systems face challenges in balancing fast writing speed and high reliability with large storage capacity and low cost, particularly in applications requiring multiple memory cell modes like SLC, MLC, TLC, and QLC.
Innovation Solution
A memory system and operation method that utilizes a peripheral circuit to determine additional page data based on a prefix command, allowing flexible configuration of memory cells to achieve multiple modes, including SLC, MLC, TLC, and QLC, by performing logical operations on page data to generate additional data states, thereby optimizing storage usage and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NAND memory uses single-level cells, then writing speed and reliability are improved, but storage capacity decreases and cost increases
Solution Approach 1:
The memory system dynamically configures memory cells between SLC and MLC modes based on operational requirements. The controller can switch between single-level and multi-level cell operations, allowing the system to optimize between reliability and storage capacity depending on the specific task or application scenario.
Solution Approach 2:
The invention changes the operational parameters of memory cells by implementing both SLC and MLC modes within the same memory system. By adjusting the programming voltage levels and data encoding schemes, the system can transform memory cell behavior between high-reliability single-bit storage and high-capacity multi-bit storage configurations.
2Quantity of substance
If NAND memory uses multi-level cells, then storage capacity and cost are improved, but writing speed and reliability decrease
Solution Approach 1:
The memory system employs dynamic mode switching between MLC and SLC operations. When high writing speed is required, the system can operate in SLC mode with simplified programming sequences. When storage capacity is the priority, it switches to MLC mode, thus dynamically balancing speed and capacity based on real-time requirements.
Solution Approach 2:
The memory system segments its operation into different modes and regions. It can divide the memory space into SLC regions for high-speed critical data and MLC regions for bulk storage, allowing simultaneous optimization of both writing speed and storage capacity across different portions of the memory system.
3Adaptability or versatility
If memory system supports multiple cell modes, then adaptability is improved, but device complexity increases
Solution Approach 1:
The memory controller is designed with universal functionality to handle both SLC and MLC operations through a unified command interface. The same basic programming and reading circuits are used in both modes, with the controller intelligently adapting the operational parameters rather than requiring completely separate control paths for each mode.
Solution Approach 2:
The memory system implements self-service through automatic mode detection and configuration. The controller can autonomously determine the optimal operating mode based on the data characteristics and system state, reducing the need for complex external control logic and simplifying the overall system architecture.
Data Source
AI summary
Embodiments of the present disclosure disclose a memory system and operation method thereof, a memory controller and a memory. The memory system includes a memory. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, and m is a positive integer greater than 1. The operation method includes: determining, by the peripheral circuit, (n+1)th group of page data according to a received prefix command and received n groups of page data, wherein n is a positive integer, and n+1 is a positive integer less than or equal to m; and writing the n groups of page data and the (n+1)th group of page data into the memory cell array to generate 2n different data states in the memory cell array.