NAND Memory Patrol with Expanding Block Voltage Coverage
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Solution Overview
Problem
Existing NAND-type flash memory systems face challenges in efficiently managing and maintaining the health of memory cells, leading to potential read errors and performance degradation over time.
Innovation Solution
A memory system with a controller that performs a patrol operation, including a dummy read process, to proactively manage memory blocks by applying varying voltages, increasing the number of blocks addressed during a second operation compared to a first operation, thereby enhancing the health and reliability of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a patrol operation with dummy read process is performed to monitor memory cell health, then read errors are reduced and reliability is improved, but processing time and operational complexity increase
Solution Approach 1:
The patrol operation performs dummy read processes proactively before actual read operations occur. By continuously monitoring memory cell health status through periodic dummy reads, the system detects potential failures early and can perform preventive actions such as data migration or error correction, thereby preventing read errors before they affect actual data operations.
Solution Approach 2:
The memory system performs self-diagnosis and self-monitoring through the patrol operation. The controller automatically executes dummy read processes to assess memory cell health without requiring external intervention, enabling the system to maintain its own reliability and detect degradation trends over time.
2Reliability
If varying voltages are applied to all memory cells in selected blocks during patrol operation, then memory cell health is maintained and read errors are reduced, but energy consumption increases
Solution Approach 1:
The patrol operation applies varying voltages selectively to specific memory blocks that are designated as patrol targets, rather than uniformly to all memory cells in the entire memory device. This localized approach allows the system to monitor and maintain health status of critical or frequently accessed blocks while conserving energy by excluding less critical blocks from the patrol process.
Solution Approach 2:
The system performs patrol operations on a subset of memory blocks rather than all blocks simultaneously. By selecting specific patrol target blocks based on usage patterns or risk assessment, the system achieves sufficient monitoring coverage to maintain reliability while reducing the overall energy burden compared to comprehensive full-array patrol operations.
3Reliability
If the number of blocks addressed in the second operation is increased compared to the first operation, then memory system coverage and reliability are improved, but device complexity and processing overhead increase
Solution Approach 1:
The patrol operation divides memory blocks into different categories or groups, with the second operation addressing a larger set of blocks including both patrol target blocks and additional blocks. This segmented approach allows systematic expansion of coverage from a core set of critical blocks to a broader set, managing complexity through organized progression rather than random or simultaneous access to all blocks.
Solution Approach 2:
The set of addressed blocks is dynamic and adaptive, with the second operation flexibly expanding beyond the first operation's scope based on detected needs. The patrol operation can adjust which blocks are targeted in subsequent operations based on health status, access patterns, or error rates, allowing the system to optimize the balance between coverage and complexity in response to actual memory conditions.
Data Source
AI summary
According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.