NAND Memory Programming Method Reducing Back Pattern Effect
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Solution Overview
Problem
Current programming methods for NAND memory arrays face issues with threshold voltage offset due to the back pattern effect, leading to program disturbance as channel voltage is blocked by memory cells with high threshold voltage.
Innovation Solution
A programming method that involves transmitting a first voltage from the common source line to the first ends of memory cell strings during a first period, floating the second ends, and then applying programming and passing voltages to the second ends during a second period to inhibit programming of one string while sequentially programming the other, thereby pre-increasing the channel voltage and reducing program disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are programmed sequentially from one side of the NAND memory array adjacent to a common source line, then programming can be completed, but threshold voltage offset occurs due to back pattern effect causing program disturbance
Solution Approach 1:
The patent applies preliminary action by pre-increasing the channel voltage of non-programmed memory cell strings before programming operations. A pre-charge operation is performed to raise the channel voltage of non-selected strings to a high level, which prevents the back pattern effect from causing threshold voltage offset during subsequent programming. This preliminary voltage preparation eliminates program disturbance before it can occur.
Solution Approach 2:
The patent changes the voltage parameter of non-programmed memory cell strings from a normal state to a pre-charged high voltage state. By dynamically adjusting the channel voltage of non-selected memory cell strings to a higher level before programming operations, the patent prevents threshold voltage offset caused by the back pattern effect, thereby resolving the technical contradiction.
2Reliability
If programming order is changed to prevent back pattern effect, then threshold voltage offset is reduced, but channel voltage of non-programmed memory cells is blocked by high threshold voltage cells causing program disturbance
Solution Approach 1:
The patent performs a pre-charge operation before programming to preliminarily increase the channel voltage of non-programmed memory cell strings. This preliminary action ensures that even when programming order is changed, the non-selected strings maintain sufficient channel voltage and are not blocked by high threshold voltage cells, thereby preventing program disturbance.
Solution Approach 2:
The patent dynamically changes the channel voltage parameter of non-programmed memory cell strings by applying pre-charge voltages. This parameter change ensures that non-selected memory cell strings maintain high channel voltage throughout the programming process, preventing the blocking effect that would otherwise cause program disturbance.
3Reliability
If common source line voltage is increased to prevent program disturbance, then channel voltage is maintained, but additional complexity is introduced to voltage control
Solution Approach 1:
The patent segments the voltage control into two independent parts: programmed memory cell strings receive programming voltages while non-programmed strings receive pre-charge voltages through the common source line. This segmentation allows selective voltage application without requiring complex individual control of each memory cell string, thereby maintaining reliability while limiting the increase in device complexity.
Data Source
AI summary
A memory device and a programming method thereof are provided, and the programming method for the memory device includes following steps. During a first period, a first voltage from a common source line is transmitted to first ends of a first memory cell string and a second memory cell string, and second ends of the first and the second memory cell strings are floated. During a second period, the first ends of the first and the second memory cell strings are floated, a second voltage and a third voltage are respectively transmitted to the second ends of the first and the second memory cell strings, and a programming voltage and a plurality of passing voltages are applied, so as to inhibit programming of the first memory cell string and sequentially program a plurality of memory cells in the second memory cell string from a second side of a memory array.