3D NAND Memory Page Programming Sequence for Data Integrity
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Solution Overview
Problem
In semiconductor memory devices, especially in three-dimensional array structures, there is a challenge in maintaining data integrity and reliability due to the interference between least significant bit and most significant bit programming, which affects the threshold voltage distribution and increases the error probability of stored data, particularly for multi-bit storage.
Innovation Solution
A method of operating semiconductor memory devices that involves performing least significant bit programs on pages of one cell string group, followed by most significant bit programs, with specific distance considerations between page groups and the common source line to minimize interference and enhance data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If least significant bit and most significant bit programs are performed simultaneously or in arbitrary order, then programming speed is improved, but data integrity and reliability deteriorate due to interference between programming operations
Solution Approach 1:
The patent applies preliminary action by performing least significant bit (LSB) programming to pages closer to the common source line before performing most significant bit (MSB) programming to pages farther from the common source line. This sequencing ensures that pages more susceptible to interference from subsequent MSB programming are programmed first, preventing degradation of previously programmed data and maintaining threshold voltage distribution integrity.
2Adaptability or versatility
If pages farther from the common source line are programmed first, then programming order flexibility is improved, but error probability increases due to greater interference impact on subsequently programmed pages
Solution Approach 1:
The patent applies local quality by differentiating the programming sequence based on the spatial location of pages relative to the common source line. Pages closer to the common source line (which are more susceptible to interference) receive LSB programming first, while pages farther away receive MSB programming first. This location-dependent sequencing strategy optimizes reliability by accounting for the varying interference characteristics of different page groups.
3Device complexity
If threshold voltage distribution is not carefully controlled during multi-bit programming, then programming complexity is reduced, but manufacturing precision deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the multi-bit programming process into distinct sequential stages: first performing LSB programming on specific page groups, then performing MSB programming on other page groups. This segmentation of the programming process into ordered phases enables precise control over threshold voltage distribution changes, ensuring that each bit level is programmed under controlled conditions that prevent interference with previously programmed bits.
Data Source
AI summary
A semiconductor memory device is operated by, inter alia, performing least significant bit programs for pages in a first page group, performing least significant bit programs for pages in a second page group, and performing most significant bit programs for the pages in the first page group. The distance between the second page group and the common source line is greater than that between the first page group and the common source line.