NAND Memory Data Randomization via Linear Feedback Shift Register
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Solution Overview
Problem
Existing semiconductor memory devices face reliability issues due to data interference in NAND cells, as data written to the same blocks are not adequately randomized, leading to potential degradation and reduced memory performance.
Innovation Solution
A semiconductor memory device with a controller that employs a linear feedback shift register to randomize data by selecting an initial value based on the memory address, using a primitive polynomial to generate pseudo-random numbers, ensuring randomness and minimizing interference between memory cells by setting the period of random number generation to exceed the block size, thereby reducing repeated writes to the same memory locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written to NAND cells without randomization, then the writing process is simple and fast, but data interference occurs and reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by randomizing data before it is written to the NAND cells. The randomization is performed in advance using a linear feedback shift register that generates pseudo-random sequences based on the memory address, ensuring that data is transformed prior to storage to prevent interference and improve reliability.
Solution Approach 2:
The patent introduces an intermediary element - a linear feedback shift register - that acts as a mediator between the data to be stored and the NAND cells. This intermediary transforms the original data into a randomized form, preventing direct data interference in the memory cells while maintaining the ability to retrieve and decode the original information.
2Reliability
If a random number generator is used to randomize data, then data randomness improves, but the circuit complexity and period limitations worsen
Solution Approach 1:
The patent changes the parameters of the randomization system by using a linear feedback shift register with a specific configuration (n registers providing a period of 2^n - 1) that is tailored to match the NAND memory block size. This parameter optimization ensures sufficient randomness while keeping the circuit complexity manageable and the period adequate for the memory structure.
3Device complexity
If the period of random number generation is short, then the circuit is simpler, but repeated writes to the same block cause interference
Solution Approach 1:
The patent optimizes the period parameter of the random number generator by configuring the linear feedback shift register to have a period of 2^n - 1, where n is the number of registers. This period is specifically chosen to exceed the NAND memory block size, ensuring that the same pseudo-random sequence does not repeat within a single block, thereby preventing data interference while maintaining circuit simplicity.
Data Source
AI summary
A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n-1 bytes, n being a number of registers included in the linear feedback shift register circuit.