Multi-Stage NAND Memory Read Control with Predicted Valley Voltages
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Solution Overview
Problem
The accuracy of reading data stored in NAND memory cells is affected by changes in stored charge over time and repeated read operations, leading to inaccuracies in data retrieval.
Innovation Solution
A memory device and system that utilize a peripheral circuit to determine a predicted valley voltage in multiple stages, adjusting read voltages to improve data reading accuracy through a process of adjusting target read voltages until a preset condition is met, enabling error correction decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If read voltage is increased to improve reading speed, then reading speed is improved, but reading accuracy deteriorates due to charge changes in memory cells
Solution Approach 1:
The patent applies preliminary action by performing multiple read operations at different voltages before final data retrieval. The peripheral circuit conducts preliminary reads at various voltages to detect charge status and predict valley voltages, then uses this information to determine the optimal read voltage for accurate data reading, thus preparing in advance to avoid accuracy loss.
Solution Approach 2:
The patent implements feedback by using read results from preliminary operations to adjust subsequent read voltages. The peripheral circuit monitors the state of memory cells through initial reads, feeds back this information to determine charge changes, and dynamically adjusts the read voltage accordingly to maintain both speed and accuracy.
2Measurement precision
If multiple read operations are performed to improve reading accuracy, then reading accuracy is improved, but reading time increases
Solution Approach 1:
The patent applies dynamics by making the read process adaptive rather than static. The system dynamically adjusts the number and voltage of read operations based on real-time detection of memory cell states. When charge changes are detected, the system performs additional reads; when stable, it uses fewer reads, thus optimizing the balance between accuracy and time.
Solution Approach 2:
The patent changes parameters (read voltage levels and number of read operations) based on detected memory cell conditions. The peripheral circuit adjusts read voltage parameters dynamically according to charge status, using higher voltages when needed and reducing read operations when memory cells are stable, thereby balancing accuracy improvement with time consumption.
3Measurement precision
If read voltage is adjusted frequently to maintain accuracy, then reading accuracy is maintained, but system complexity increases
Solution Approach 1:
The patent implements self-service by enabling the memory system to automatically adjust its own read parameters without external intervention. The peripheral circuit autonomously detects charge changes in memory cells, predicts valley voltages, and determines appropriate read voltages independently, reducing the need for complex external control mechanisms while maintaining accuracy.
Solution Approach 2:
The patent introduces an intermediary component - the peripheral circuit - that mediates between the memory cell array and the control logic. This intermediary handles the complex tasks of detecting charge changes, predicting valley voltages, and determining read parameters, thereby isolating the complexity from the main control system and simplifying overall system architecture.
Data Source
AI summary
Examples of the present disclosure provide a memory device, memory system, memory controller and operating method thereof. The memory device includes a memory cell with multiple storage bits, a preset number of the memory cells form one code word, and the multiple storage bits correspond to multiple pages respectively. The multiple stages include a first stage and a second stage. The peripheral circuit of the memory device is configured to: obtain a predicted valley voltage in the first stage in accordance with the corresponding first result at the target read voltage in the first stage; obtain the predicted valley voltage in the second stage in accordance with the predicted valley voltage in the first stage; and perform a first read operation on at least one code word with the predicted valley voltage in the first stage and the predicted valley voltage in the second stage.