NAND Memory Read-Voltage Tuning for Accurate Data Retrieval
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Solution Overview
Problem
The accuracy of data reading in NAND type memories is affected by the variation of stored charges over time and repeated read operations, leading to inaccuracies in data retrieval.
Innovation Solution
A memory device and system that perform multiple adjustments on a target read voltage to determine an inflection point and a target valley bottom voltage, using a peripheral circuit to refine the read operation by iteratively adjusting voltages to minimize flipped bits and stabilize data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed read voltage is used for data reading, then the reading operation is simple and fast, but the data reading accuracy deteriorates due to charge variation in memory cells
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed read voltage to a dynamic read voltage that is automatically adjusted based on the actual threshold voltage distribution of memory cells. The system performs multiple voltage adjustments (M first adjustments with first step, then N second adjustments with second step) to converge on an optimal read voltage, making the reading operation adaptive to charge variations while maintaining computational simplicity through automated convergence.
Solution Approach 2:
The patent implements parameter changes by systematically varying the read voltage parameter through multiple adjustment steps. The peripheral circuit changes the voltage parameter from an initial value through M adjustments with a first step size to find an inflection point, then performs N adjustments with a smaller second step size to reach the valley bottom, thereby optimizing the voltage parameter to match actual memory cell characteristics.
2Measurement precision
If multiple voltage adjustments are performed to improve reading accuracy, then data reading accuracy is improved, but the time required for reading operations increases
Solution Approach 1:
The patent applies segmentation by dividing the voltage adjustment process into two distinct phases: M first adjustments with a larger first step size to rapidly approach the inflection point, followed by N second adjustments with a smaller second step size to precisely reach the valley bottom. This segmentation allows the system to achieve high accuracy while minimizing total adjustment iterations by using coarse adjustment initially and fine adjustment only when necessary.
Solution Approach 2:
The patent implements partial action by performing a limited number of voltage adjustments (M and N) rather than exhaustive search. The peripheral circuit stops adjusting when the valley bottom is sufficiently approached, using the inflection point as an intermediate target that provides adequate accuracy without requiring complete exhaustion of all possible voltage values, thus balancing accuracy and time efficiency.
3Reliability
If the read voltage is adjusted to match memory cell threshold voltage, then bit flip errors are reduced, but the complexity of determining the optimal voltage increases
Solution Approach 1:
The patent applies self-service by enabling the peripheral circuit to automatically determine the optimal read voltage through self-contained voltage adjustment operations. The system uses the memory cells themselves as the reference for voltage adjustment, where the inflection point and valley bottom are identified through the cells' actual electrical characteristics during reading operations, eliminating the need for external calibration equipment or complex pre-characterization processes.
Solution Approach 2:
The patent implements feedback by using the reading results at each voltage adjustment step to guide subsequent adjustments. The peripheral circuit monitors the number of flipped bits at each voltage level and uses this feedback information to determine when the valley bottom has been reached, creating a closed-loop system that automatically converges on the optimal read voltage based on actual reading performance.
Data Source
AI summary
Examples of the present disclosure disclose a memory device, a memory system, a memory controller, and a method. The memory device may include a memory cell array with a plurality of memory cells. The memory device may include peripheral circuit coupled with the memory cell array and configured to: perform M first adjustments on a target read voltage of at least one code word with a first step, and acquire M first results corresponding to M read voltages obtained after the M first adjustments respectively; take the minimum first result in the M first results as an inflection point value; perform N second adjustments on the inflection point voltage with a second step, and acquire N first results corresponding to N read voltages obtained after the N second adjustments respectively; and determine a target valley bottom voltage according to the acquired N first results.