3D NAND Memory Block Segmentation via Dielectric Trenches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As 3D NAND technology advances towards higher densities and capacities, the increasing number of word line layers leads to longer read and erase times, longer data transfer times, and lower storage efficiency due to larger block sizes and shared control gates that induce longer operation times.
Innovation Solution
The introduction of first and second dielectric trench structures positioned in the bottom and top select gate layers, respectively, to separate these layers into sub-portions, allowing for independent operation of sub-blocks and improving channel structure density by dividing the block into three functional sub-blocks, thereby reducing programming, reading, and erasing times, and enhancing data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word line layers is increased to achieve higher storage capacity, then storage capacity is improved, but read and erase times increase
Solution Approach 1:
The block is divided into multiple sub-blocks using dielectric trench structures that physically separate the select gate layers. This segmentation allows independent operation of sub-blocks, enabling parallel read and erase operations, thereby reducing overall operation times while maintaining high storage capacity through the increased number of word line layers.
2Quantity of substance
If the number of word line layers is increased to achieve higher storage capacity, then storage capacity is improved, but data transfer time increases
Solution Approach 1:
By segmenting the block into sub-blocks with independent select gate portions, data can be transferred from multiple sub-blocks simultaneously through parallel data lines. This increases the effective data transfer rate while accommodating the higher storage capacity provided by additional word line layers.
3Quantity of substance
If the number of word line layers is increased to achieve higher storage capacity, then storage capacity is improved, but storage efficiency decreases
Solution Approach 1:
The dielectric trench structures divide the select gate layers into sub-portions that can independently control different sub-blocks. This enables selective operation where only portions of the high-capacity storage array need to be accessed at any given time, improving storage efficiency by avoiding unnecessary operations on the entire large-capacity block.
4Loss of time
If dielectric trench structures are introduced to separate select gate layers into sub-portions, then operation times are reduced, but device complexity increases
Solution Approach 1:
The dielectric trench structures provide physical separation that enables independent control of sub-blocks through sub-portions of the select gate layers. This segmentation allows parallel and selective operations that reduce operation times, while the modular nature of the trenches makes the increased complexity manageable through standardized fabrication processes.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a stack of word line layers and insulating layers that are stacked alternatingly over a substrate. The semiconductor device also includes a first dielectric trench structure. The first dielectric trench structure is positioned in a bottom select gate (BSG) layer of the word line layers to separate the BSG layer and extends in a first direction of substrate. The semiconductor device further includes a second dielectric trench structure. The second dielectric trench structure is positioned in a top select gate (TSG) layer of the word line layers to separate the TSG layer and extends in the first direction of the substrate. The second dielectric trench structure is offset from the first dielectric trench structure in a second direction of the substrate that is perpendicular to the first direction.