Error Correction in NAND Memory Using Selective SGD Reads
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Solution Overview
Problem
Non-volatile memory systems, particularly NAND memory technologies, face reliability issues due to voltage shifts and word line shorts, leading to increased bit errors, decode time degradation, and potential data loss, which existing error correction methods struggle to address efficiently.
Innovation Solution
The method involves determining bit error ratios and performing selective read operations using soft bit data to generate and apply appropriate correction data, such as through SGD read operations and LDPC corrections, to correct errors associated with voltage downshift, upshift, and word line shorts, thereby improving error correction efficiency and data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods are used, then data integrity is maintained, but decode time increases and performance degrades
Solution Approach 1:
The patent applies partial action by selectively performing SGD read operations and generating soft bit data only when bit error ratios fall within specific threshold ranges. Instead of always performing full error correction procedures, the system performs correction actions only when necessary based on measured error levels, thereby reducing unnecessary decode time while maintaining data integrity when errors are present
Solution Approach 2:
The patent changes the parameter of error correction approach based on the measured bit error ratio. When the BER is between first and second thresholds, the system uses SGD read operations with soft bit data generation. When BER exceeds different threshold ranges, different correction strategies are applied. This dynamic parameter adjustment optimizes decode time by matching the correction intensity to the actual error level
2Productivity
If selective error correction operations are performed, then error correction efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the error correction process into distinct operational phases based on bit error ratio thresholds. The control logic divides error handling into multiple pathways: monitoring phase, threshold comparison phase, SGD operation phase, and correction phase. This segmentation makes the complex control logic more manageable and implementable by breaking it into discrete, condition-based steps
3Reliability
If memory blocks are retired early, then data reliability is maintained, but storage capacity is reduced
Solution Approach 1:
The patent performs preliminary error detection and correction actions before memory blocks reach critical failure points. By continuously monitoring bit error ratios and applying corrective measures (SGD reads, soft bit data generation, LDPC corrections) when errors are detected but still within correctable ranges, the system prevents errors from escalating to uncorrectable levels that would require block retirement, thereby extending block lifespan and maintaining storage capacity
Data Source
AI summary
A method for error correction in a memory system includes determining a bit error ratio for a memory block of the memory system during a read operation. The method further includes determining whether the bit error ratio is between a first threshold and a second threshold. The method further includes based on a determination that the bit error ratio is between the first threshold and the second threshold, performing a select gate drain (SGD) read operation on a SGD word line of the memory block. The method further includes generating first soft bit data using SGD data corresponding to the SGD read operation. The method further includes performing a low-density parity-check correction using the first soft bit data on the memory block.