3D NAND Memory Layout With Shifted Sense Amplifiers for Faster Reads
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Solution Overview
Problem
Existing NAND flash memory devices face challenges in efficiently accessing and reading data from memory cells due to limitations in their architectural design, which affects performance and efficiency.
Innovation Solution
The memory device incorporates a novel architecture where a substrate with memory cells is bonded to a substrate with CMOS circuits, featuring a sense amplifier module with shifted sense amplifier regions and transfer regions, allowing for improved data access and reading capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional NAND flash memory architecture is used, then the device structure is simple, but data access and reading efficiency is poor
Solution Approach 1:
The memory device is divided into two separate substrates: a first substrate containing memory cells and a second substrate containing CMOS circuits. This segmentation allows independent optimization of each substrate's function, improving data access efficiency while managing complexity through modular architecture
Solution Approach 2:
The patent transitions from a planar single-substrate architecture to a three-dimensional stacked architecture where memory cells and CMOS circuits are vertically integrated on separate substrates. This dimensional change enables improved signal routing and reduces interference, enhancing reading efficiency without proportionally increasing complexity
2Quantity of substance
If memory cells are densely packed, then storage capacity increases, but data reading performance deteriorates
Solution Approach 1:
A dedicated sense amplifier module is introduced as an intermediary component on the CMOS substrate to handle signal amplification and data reading operations. This intermediary handles the complex task of reading from densely packed memory cells, maintaining reading performance while enabling high storage capacity through efficient signal processing
Solution Approach 2:
By moving CMOS circuits to a separate substrate in the vertical dimension, the patent creates independent signal paths that can handle high-density memory arrays without interference. The sense amplifier module processes signals from multiple memory cells simultaneously, maintaining reading performance despite increased storage capacity
3Productivity
If sense amplifier regions are traditionally arranged, then layout is simple, but electrical coupling between memory cells and CMOS circuits is inefficient
Solution Approach 1:
The sense amplifier regions are asymmetrically positioned on the CMOS substrate to optimize electrical coupling with the memory cell substrate. The asymmetric layout allows shorter and more direct signal paths between sense amplifiers and memory cells, improving electrical coupling efficiency while the irregular arrangement naturally manages routing complexity
Data Source
AI summary
According to one embodiment, a memory device includes a substrate, a memory layer, and a circuit layer. The memory layer includes first to third regions arranged in a first direction. The circuit layer includes first and second transfer regions, and first and second sense amplifier regions. The first and second transfer regions are shifted in the first direction and arranged in a second direction. In a third direction, the first sense amplifier region overlaps the first region, and the second sense amplifier region overlaps the second region. The first sense amplifier region and the first transfer region are arranged in the first direction, and the second sense amplifier region and the second transfer region are arranged in the first direction.