3D NAND Memory Block Isolation via Dielectric Slits
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Solution Overview
Problem
Conventional stacked memory technology faces challenges in increasing capacity with high manufacturing efficiency due to issues like short circuits between word line electrode layers of adjacent blocks, caused by residual electrode layers beside slit sidewalls during staircase patterning.
Innovation Solution
A semiconductor memory device with a stacked body of conductive and dielectric layers, where memory cells are formed with silicon pillars and charge storage layers, and memory strings are divided into blocks by slits with an interlayer dielectric film, ensuring each block is surrounded by slits in a closed pattern to prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If staircase patterning is used to create electrical contact to word line electrode layers, then electrical contact is achieved, but residual electrode layers may remain beside slit sidewalls causing short circuits between adjacent blocks
Solution Approach 1:
An interlayer dielectric film is introduced as an intermediary material to fill the slit and isolate residual electrode layers from adjacent blocks. This dielectric barrier prevents electrical short circuits while allowing the staircase patterning process to proceed for electrical contact formation.
Solution Approach 2:
The harmful residual electrode layers are effectively removed from the electrical pathway by filling the slit with interlayer dielectric material. This extraction of the conductive path prevents short circuits between adjacent blocks while preserving the intended electrical contacts.
2Manufacturing precision
If conventional stacked memory technology is used with many manufacturing steps per layer, then manufacturing precision can be maintained, but manufacturing efficiency decreases and capacity scaling is limited
Solution Approach 1:
Multiple layer formation operations are merged into a single collective patterning process. The gate electrode layers and interlayer dielectric layers are alternately stacked and then collectively patterned in one etching step, dramatically reducing the number of manufacturing steps while maintaining precision through the self-aligned nature of the process.
Solution Approach 2:
The memory structure transitions from planar to three-dimensional stacked architecture. By stacking gate electrode layers and interlayer dielectric layers vertically and forming holes through the entire stack, the invention achieves higher capacity in the vertical dimension while using fewer manufacturing steps compared to conventional planar approaches.
Data Source
AI summary
A semiconductor memory device includes: a semiconductor substrate; a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked, the stacked body being provided on the semiconductor substrate; a semiconductor layer provided inside a hole formed through the stacked body, the semiconductor layer extending in stacking direction of the conductive layers and the dielectric layers; and a charge storage layer provided between the conductive layers and the semiconductor layer. The stacked body in a memory cell array region including a plurality of memory strings is divided into a plurality of blocks by slits with an interlayer dielectric film buried therein, the memory string including as many memory cells series-connected in the stacking direction as the conductive layers, the memory cell including the conductive layer, the semiconductor layer, and the charge storage layer provided between the conductive layer and the semiconductor layer, and each of the block is surrounded by the slits formed in a closed pattern.