NAND Memory Speed Control for Lifetime Extension
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Solution Overview
Problem
Semiconductor memory apparatuses face challenges in maintaining maximum performance over a five-year durable use period due to the limited number of rewrite times in NAND memory, particularly with MLC-type NAND memory, where write speed and rewrite times are lower than SLC-type, and the existing methods for estimating lifetime and controlling write speed are inefficient, leading to potential premature end of lifetime due to bad blocks and varying usage conditions.
Innovation Solution
A semiconductor memory apparatus with a speed control unit that dynamically calculates the total writable amount and ideal write pace, adjusting write performance to prevent exceeding the ideal write pace, and controls data transmission speed to ensure the write pace does not exceed the permissible value, thereby extending the durable use period by managing surplus capacity and bad blocks effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written continuously at maximum write speed in NAND memory, then productivity is improved, but the number of rewrite times is exceeded leading to premature end of lifetime
Solution Approach 1:
The patent implements dynamic write speed control that adjusts the write pace based on real-time monitoring of remaining rewrite times and bad block counts. The speed control unit dynamically modifies the write speed to ensure the accumulated write amount does not exceed the ideal write pace calculated from lifetime requirements, thereby maintaining both productivity and extended durability throughout the five-year period.
Solution Approach 2:
The system incorporates feedback mechanisms where the speed control unit continuously monitors the actual write pace, compares it against the ideal write pace derived from remaining rewrite times and bad block statistics, and adjusts the write speed accordingly. This closed-loop control ensures that write operations remain within safe limits while maximizing utilization of the memory's rewrite capacity.
2Quantity of substance
If MLC-type NAND memory is used to increase storage capacity, then quantity of substance is improved, but write speed and number of rewrite times are reduced compared to SLC-type
Solution Approach 1:
The patent changes the operational parameters of MLC-type NAND memory by implementing dynamic write speed adjustment based on remaining rewrite times and bad block counts. Instead of operating at constant maximum speed, the system adapts the write pace to match the actual endurance characteristics of MLC memory, thereby optimizing both the utilization of storage capacity and the sustained write performance over the device's lifetime.
3Loss of time
If write speed is increased to improve productivity, then loss of time is reduced, but the accumulated write amount exceeds the ideal write pace leading to premature wear
Solution Approach 1:
The system performs preliminary calculation of the ideal write pace based on required lifetime, remaining rewrite times, and bad block statistics before executing write operations. The speed control unit uses this pre-calculated ideal pace as a guide to limit the accumulated write amount, ensuring that write operations proceed as fast as possible without exceeding the safe threshold that would lead to premature wear or bad block formation.
Data Source
AI summary
According to one embodiment, a semiconductor memory apparatus includes a memory and a speed control unit. The speed control unit calculates a time-varying behavior of a permissible value of an accumulated amount of data written in the non-volatile semiconductor memory, where, after a start of a guaranteed period, data is written in the memory at a constant write speed so that the permissible value at an end time of the guaranteed period is equal to a sum of a first capacity and a second capacity. The first capacity is an accumulated amount of data written in the memory. The second capacity is an accumulated amount of data which is writable in the memory in a remaining time of the guaranteed period based on remaining rewritable times of existing blocks. The speed control unit controls a transmission speed of data from a host based on the permissible value.