3D NAND Memory Standby Charge Loss Mitigation
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Solution Overview
Problem
In 3D NAND flash memory devices, charge loss during the standby state is a significant challenge due to defects caused by ion implantation, leading to inferior data retention and increased memory cell threshold voltage shifts, which existing solutions fail to adequately address under system resource constraints.
Innovation Solution
A memory device with a control circuit that selectively applies positive bias potentials to access lines during standby through self-boosting or charging a common p-well, combined with a leakage compensation circuit to maintain access line voltage and prevent charge loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase memory density, then memory capacity per area increases, but charge loss during standby state increases due to ion implantation defects
Solution Approach 1:
The patent applies different voltage conditions to different parts of the memory system during standby state. Specifically, it maintains a first voltage on bit lines and a second voltage on word lines, creating localized voltage conditions that reduce charge loss in miniaturized cells while preserving the high density achieved through small cell dimensions.
Solution Approach 2:
The patent proactively applies voltage maintenance circuits and compensation mechanisms before charge loss can significantly degrade data retention. By continuously or periodically refreshing the charge state and compensating for ion implantation defects during standby, it prevents the accumulation of charge loss that would otherwise occur in reduced-size memory cells.
2Reliability
If voltage is continuously applied to access lines to prevent charge loss, then data retention improves, but power consumption increases
Solution Approach 1:
Instead of continuous voltage application, the patent employs periodic or conditional voltage maintenance on access lines during standby state. The voltage refresh and compensation operations are performed at intervals or only when charge loss is detected, rather than continuously, thereby reducing overall power consumption while maintaining adequate data retention.
Solution Approach 2:
The patent incorporates voltage maintenance functionality directly into the memory device's internal circuits, allowing the system to self-refresh and self-compensate for charge loss without requiring continuous external power intervention. This integrated approach optimizes power usage by performing maintenance operations only when necessary.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces charge loss during standby, enhancing data retention and maintaining memory performance even under limited system resources, by stabilizing the access line voltage and preventing undesired charge gain.
Implementation Method 1
a control circuit configured to couple, in a standby state, a supply voltage (VCC) to the access line to charge the access line to a positive bias potential
Data Source
AI summary
Discussed herein are systems and methods for charging an access line to a non-volatile memory cell during a standby state, such as to prevent or mitigate standby-state charge loss. An embodiment of a memory device comprises a memory cell, a string driver circuit, and a charging circuit. The string driver circuit is coupled to the memory cell via a local word line, and has a common p-well. The charging circuit, in response to a voltage of a global word line of the memory device falling below a reference voltage during a standby state, couple a supply voltage to the common p-well of the string driver circuit to charge the global word line to a positive bias potential. The memory device includes a leakage compensation circuit to compensate for the junction leakage.