NAND Memory Mapping With Binary-to-Ternary LDPC Coding
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Solution Overview
Problem
Existing techniques face challenges in effectively mapping and error correction for n-level NAND flash memory devices where n is not a multiple of 2, particularly in managing binary information storage and retrieval with high endurance and minimizing error propagation.
Innovation Solution
Implementing a ternary low-density parity check (LDPC) module and binary to ternary mapping techniques, which convert binary strings to ternary format for error correction and storage in 3-level NAND memory, using a converter to map binary data to ternary symbols and applying parity checks to reduce error propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cells (MLCs) are used to increase storage density, then storage capacity is improved, but error propagation increases and endurance decreases
Solution Approach 1:
The patent introduces a binary-to-ternary converter as an intermediary component between the binary data source and the multi-level NAND memory. This converter transforms binary data into ternary symbols, enabling more efficient mapping to MLC states while reducing error propagation through the mathematical properties of ternary representation and LDPC coding.
Solution Approach 2:
The patent changes the data representation parameter from binary (base-2) to ternary (base-3) to better match the physical states of multi-level memory cells. This parameter change allows 3-level NAND memory to store log2(3) ≈ 1.58 bits per cell instead of 1 bit, increasing storage density while the LDPC code maintains reliability by correcting errors that occur during read/write operations.
2Device complexity
If binary data is directly mapped to multi-level cells, then device complexity is reduced, but error correction capability is insufficient
Solution Approach 1:
The patent introduces a binary-to-ternary converter as an intermediary component between the binary data source and the multi-level NAND memory. This converter transforms binary data into ternary symbols, enabling more efficient mapping to MLC states while reducing error propagation through the mathematical properties of ternary representation and LDPC coding.
Solution Approach 2:
The patent applies preliminary action by performing error correction coding (LDPC) on the binary data before converting it to ternary format and writing to memory. This pre-processing step ensures that error correction capabilities are built into the data structure before storage, rather than requiring complex post-read correction mechanisms.
3Reliability
If ternary conversion and LDPC coding are implemented, then error correction is improved, but device complexity increases
Solution Approach 1:
The patent segments the error correction function into distinct components: a binary-to-ternary converter that handles format transformation, and a separate LDPC encoder that handles error correction coding. This segmentation allows each component to be optimized independently and simplifies the overall system architecture by separating concerns between data representation and error protection.
Data Source
AI summary
Apparatus, systems, and methods to manage NAND memory are described. In one embodiment, a memory controller logic is configured to apply a binary parity check code to a binary string and convert the binary string to a ternary string.