NAND Memory Programming with Threshold Voltage Verification
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Solution Overview
Problem
NAND memory devices face increased bit error rates when storing multiple bits per cell, leading to latency issues due to the need for multiple reads and error correction processes, which can hinder efficient data storage and retrieval.
Innovation Solution
The method involves determining the number of threshold voltages within specific regions of a threshold voltage distribution to assess the residual bit error rate, allowing for the decision to store additional bits only if the error rate meets certain thresholds, and performing error correction if necessary, thereby reducing the need for multiple reads and improving programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits are stored per cell to increase storage capacity, then storage density is improved, but bit error rate increases
Solution Approach 1:
The patent performs preliminary verification of previously programmed pages before programming additional bits. By checking the bit error rate of existing data and performing error correction in advance, the system ensures data integrity is maintained when increasing storage density by programming multiple bits per cell.
Solution Approach 2:
The patent implements a feedback mechanism where the bit error rate is continuously monitored during the programming process. Based on the measured error rate, the system dynamically adjusts error correction coding strength and determines whether additional error correction is needed, creating a closed-loop control system that maintains reliability while maximizing storage capacity.
2Reliability
If multiple reads and error correction processes are performed to ensure data accuracy, then reliability is improved, but latency increases
Solution Approach 1:
The patent performs error correction on previously programmed pages before programming new data, rather than waiting until the end. This preliminary error correction prevents error accumulation and reduces the need for multiple corrective reads later, thereby reducing overall latency while maintaining data accuracy.
Solution Approach 2:
The patent applies error correction selectively based on the measured bit error rate. When the error rate is below a threshold, minimal or no error correction is applied. When the error rate exceeds the threshold, enhanced error correction is performed. This partial action approach avoids unnecessary processing overhead while ensuring data accuracy when needed.
3Reliability
If error correction coding is applied to maintain acceptable bit error rate, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements adaptive error correction where the strength of error correction coding is adjusted based on the measured bit error rate. When errors are minimal, lightweight or no error correction is applied. When errors exceed thresholds, stronger error correction is activated. This selective approach maintains reliability while minimizing the complexity overhead of error correction mechanisms.
Solution Approach 2:
The patent dynamically changes error correction parameters based on the programming state and measured error rates. Different error correction codes and strengths are applied depending on the number of bits per cell and the observed error characteristics, optimizing the balance between reliability and complexity for different operating conditions.
Data Source
AI summary
A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.