NAND Memory Topology Reducing Capacitive Pin Loading
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Solution Overview
Problem
Non-volatile memory systems with large numbers of memory chips, such as NAND-based SSDs, face capacitive pin loading limitations that restrict data transfer rates due to the cumulative load on memory chip pins, making it challenging to increase data transfer frequencies.
Innovation Solution
A novel topology for memory chips is introduced, featuring a tree-like structure with a D flip-flop interface that reduces capacitive loading by allowing each memory chip to drive only a subset of other chips, and includes a switching mechanism to swap input and output pins, enabling efficient data transfer and reducing pin loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are connected in parallel to increase storage capacity, then the storage capacity increases, but the capacitive pin loading increases which limits the data transfer rate
Solution Approach 1:
The patent divides the memory system into multiple independent channels, each handling a subset of memory chips. Instead of connecting all chips to a single bus, the system segments the connection topology into hierarchical levels, where chips are grouped into channels and each channel has dedicated control logic. This segmentation reduces the capacitive load on any single control pin while maintaining high storage capacity through parallel channel operation.
Solution Approach 2:
The patent introduces a hierarchical dimension to the connection topology, moving from a flat parallel connection to a multi-level structure. Memory chips are organized in a tree-like hierarchy with multiple levels of multiplexing, where lower-level chips connect to intermediate controllers that aggregate data before passing to higher-level controllers. This dimensional change allows scaling storage capacity without proportionally increasing pin loading on any single controller.
2Device complexity
If the number of memory chips per channel is increased to reduce channel count, then system complexity decreases, but capacitive loading on each channel increases reducing signal integrity
Solution Approach 1:
The patent implements a nested hierarchical structure where memory chips are grouped into channels, channels are grouped into larger aggregates, and multiple aggregation levels exist within a single package or module. Each nesting level has its own control logic and buffering, allowing the system to manage many chips without any single controller experiencing excessive capacitive load. This nested organization maintains signal integrity at each level while supporting high chip counts overall.
3Productivity
If higher clock frequencies are used to increase data transfer rate, then productivity increases, but signal integrity deteriorates due to cumulative capacitive loading
Solution Approach 1:
The patent implements dynamic clocking strategies where different channels or chip groups can operate at different clock frequencies based on their specific loading conditions and data traffic patterns. The hierarchical structure allows flexible frequency scaling at different levels, enabling the system to achieve high overall throughput without requiring all chips to operate at maximum frequency simultaneously, thereby maintaining signal integrity.
Data Source
AI summary
A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used. The pads of the memory chip can be configurable to swap input and output pads to more efficiently form the memory chips into a package.