NAND Memory Area Effective Erase Voltage Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In non-volatile memory storage systems, the integration of low voltage components with high erase voltage components poses a challenge in terms of space conservation and read latency, as existing solutions often require additional circuitry to isolate these components, thereby increasing the overall height of the memory array and reducing available space for storage elements.
Innovation Solution
The implementation of a deep N-well region in the semiconductor substrate allows both the memory cell and peripheral circuitry regions to be placed on, ensuring that high erase voltage is applied to all terminals of low voltage transistors, thereby preventing large voltage differences and reducing the need for additional isolation components, and the use of a voltage isolation circuit to protect sense amplifier drivers from high erase voltage during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional isolation circuitry is added to protect low voltage components from high erase voltage, then reliability is improved, but device complexity and area increase
Solution Approach 1:
The patent applies equipotentiality by connecting the bulk terminals of low voltage transistors to the high erase voltage potential during erase operations. This is achieved through well taps (N-well for PMOS, P-well for NMOS) that are connected to VERA, ensuring that all transistor terminals (source, drain, gate, and bulk) are at the same high voltage potential, thereby eliminating voltage differences that could cause damage or malfunction.
2Reliability
If additional isolation circuitry is added to protect low voltage components from high erase voltage, then reliability is improved, but chip area increases
Solution Approach 1:
The patent applies equipotentiality by connecting the bulk terminals of low voltage transistors to the high erase voltage potential during erase operations. This is achieved through well taps (N-well for PMOS, P-well for NMOS) that are connected to VERA, ensuring that all transistor terminals (source, drain, gate, and bulk) are at the same high voltage potential, thereby eliminating voltage differences that could cause damage or malfunction.
3Reliability
If additional isolation circuitry is added to protect low voltage components from high erase voltage, then reliability is improved, but read latency increases
Solution Approach 1:
The patent applies equipotentiality by connecting the bulk terminals of low voltage transistors to the high erase voltage potential during erase operations. This is achieved through well taps (N-well for PMOS, P-well for NMOS) that are connected to VERA, ensuring that all transistor terminals (source, drain, gate, and bulk) are at the same high voltage potential, thereby eliminating voltage differences that could cause damage or malfunction.
Data Source
AI summary
A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.