NAND Memory Programming Voltage Slope Control
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Solution Overview
Problem
The programming of NAND memory arrays is often affected by parasitic capacitors between floating gates and adjacent channels, which complicates the implementation of multi-level cell programming due to variations in threshold voltage distribution.
Innovation Solution
A programming method that involves a series of operations on a target memory cell and adjacent cells, including verification steps to determine the need for additional programming cycles, where the first transistor is turned on and the second transistor is turned off, and the programming voltage is incremented, to manage the influence of parasitic capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ISPP method is used to program memory cells with reduced size, then programming speed is improved, but parasitic capacitor influence increases causing threshold voltage distribution to widen
Solution Approach 1:
The patent applies preliminary action by performing verification operations on target memory cells and adjacent periphery memory cells before determining the next programming step. This advance verification allows the system to predict and prevent parasitic capacitor interference by identifying cells that require different programming treatments beforehand, thus maintaining threshold voltage distribution precision while preserving ISPP programming speed.
Solution Approach 2:
The patent implements local quality by applying different programming operations to different memory cells based on their specific states and positions. Target memory cells receive one programming operation while adjacent periphery memory cells receive different programming operations tailored to their local characteristics, preventing parasitic capacitor interference in specific localized areas without affecting overall programming efficiency.
2Productivity
If programming voltage level is increased to improve programming efficiency, then programming speed is improved, but parasitic capacitor coupling effect is amplified
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting programming voltage parameters based on verification results. Instead of uniformly increasing voltage for all cells, the system modifies voltage application patterns selectively - applying higher voltages only where needed while using different voltage patterns for adjacent cells to minimize parasitic coupling, thus maintaining programming efficiency while reducing harmful capacitor effects.
Solution Approach 2:
The patent implements segmentation by dividing the programming process into distinct phases: verification phase, determination phase, and selective programming phase. This segmentation allows the system to identify which specific memory cells require high-voltage programming versus those that need protective low-voltage treatment, thereby applying high programming efficiency only where necessary while preventing parasitic capacitor coupling in adjacent cells.
3Manufacturing precision
If verification operations are performed on target and periphery memory cells to avoid parasitic capacitor influence, then programming precision is improved, but operation complexity increases
Solution Approach 1:
The patent applies universality by designing a multi-functional verification and control system that simultaneously handles target memory cells and adjacent periphery memory cells through integrated operations. This unified approach performs multiple functions (verification, determination, and selective programming control) within a single operational framework, improving programming precision while avoiding the complexity of separate independent processes for each cell type.
Solution Approach 2:
The patent implements feedback by using verification results from both target and periphery memory cells to determine subsequent programming operations. This feedback mechanism creates a closed-loop control system where verification data directly informs programming decisions, achieving high precision through systematic feedback-based control rather than complex open-loop procedures.
Data Source
AI summary
A programming method of a memory array is provided and includes following steps, wherein the memory array includes a target memory cell and two periphery memory cells electrically connected to a first word line. After a first programming operation is performed on the target memory cell, the target memory cell and the two periphery memory cells are verified to obtain a first verification result. Whether to perform a second programming operation or a third programming operation on the target memory cell is determined according to the first verification result. The step of performing the second programming operation or the third programming operation on the target memory cell includes: turning off a first transistor and a second transistor; and increasing a level of a passing voltage for turning on a plurality of non-target memory cells and a level of a programming voltage transmitted by the first word line.