NAND Memory Wiring Layout for Gap-Defect-Resistant Layer Bonding
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Solution Overview
Problem
Existing NAND flash memory devices face challenges in efficiently integrating multiple circuit layers and wirings, leading to issues such as gap defects and reduced reliability in data storage.
Innovation Solution
The memory device incorporates a configuration with alternating first and second wirings arranged in different directions, separated by insulating members, and includes a bonding structure with multiple layers and bonding surfaces to enhance connectivity and reduce defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple circuit layers and wirings are integrated in NAND flash memory, then storage capacity increases, but gap defects and reliability issues increase
Solution Approach 1:
A bonding pad structure is introduced as an intermediary component between the first circuit layer and second circuit layer. The bonding pad includes a first bonding pad region and a second bonding pad region that are electrically connected through a via, serving as a mediator to establish reliable electrical connections while preventing gap defects between layers.
Solution Approach 2:
The bonding pad is segmented into multiple regions: a first bonding pad region in the first circuit layer, a via connecting the layers, and a second bonding pad region in the second circuit layer. This segmentation allows each region to be optimized independently for its specific function, improving overall reliability while maintaining high storage capacity.
2Quantity of substance
If multiple circuit layers are integrated, then storage capacity increases, but manufacturing complexity increases
Solution Approach 1:
The bonding pad structure merges multiple functional elements into a unified design: the first bonding pad region, the via, and the second bonding pad region work together as an integrated electrical connection system. This merging simplifies the manufacturing process by providing a standardized interface between layers, reducing the complexity associated with integrating multiple circuit layers.
3Productivity
If wiring density is increased to improve storage efficiency, then storage capacity increases, but gap defects increase
Solution Approach 1:
The via structure serves as an intermediary that bridges the first and second circuit layers, providing a reliable electrical connection path that prevents gap defects even when wiring density is increased. This mediator ensures continuous electrical connectivity despite higher integration density.
Solution Approach 2:
The bonding pad structure extends into the vertical dimension with the via connecting different layers. This three-dimensional approach allows electrical connections to be established in the vertical dimension, relieving the horizontal wiring density constraints and enabling higher storage efficiency without increasing gap defects.
Data Source
AI summary
A memory device includes a substrate; a first circuit layer provided between the substrate and a bonding surface and including a first circuit; a second circuit layer provided above the bonding surface and including a second circuit; and a wiring layer provided above the second circuit layer and including a plurality of first wirings and a plurality of second wirings, each of the first and second wirings extending in a first direction. The plurality of first wirings are electrically connected to at least one of the first circuit or the second circuit. The plurality of second wirings are electrically connected to each other. The first wirings and the second wirings are arranged alternately in a second direction along a substrate surface of the substrate, the second direction intersecting the first direction.