NAND Memory Write Protection via Address Monitoring
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Solution Overview
Problem
NAND flash memory devices lack a write-protect feature for specific locations, posing a risk to boot sector and other sensitive software or firmware stored in them, as they can be overwritten by malicious or erroneous commands.
Innovation Solution
A system and method that monitors I/O bus commands for write operations to NAND memory devices, evaluates destination addresses, and applies a write protect signal to prevent modifications to restricted areas, ensuring that sensitive data like boot code is protected from unauthorized changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND flash memory devices are used to store boot code and firmware, then storage density and cost are improved, but write-protection capability for specific locations is lost
Solution Approach 1:
The patent introduces a memory controller as an intermediary between the processor and NAND flash memory device. This controller monitors commands destined for the memory device, evaluates whether they are restricted commands, and selectively prevents them from being asserted on restricted addresses. This mediator layer adds write-protection capability to NAND flash memory without changing the underlying memory architecture.
2Ease of operation
If write commands are allowed on all memory locations, then ease of operation is improved, but data integrity of boot sector is compromised
Solution Approach 1:
The patent implements address-based restrictions where different memory locations have different access characteristics. The memory controller evaluates destination addresses of write commands and selectively allows or prevents writes based on whether the address falls within restricted regions (such as boot sector). This enables flexible write access to non-critical areas while protecting critical data integrity in restricted areas.
Data Source
AI summary
The invention relates to a system and method for controlling implementation of a command to a NAND memory device. The method comprises: monitoring an input/output (I/O) bus connected to the NAND memory device for an assertion of a write command for the NAND memory device. Upon detection of the write command, the method evaluates a destination address associated with the write command. If the destination address is not a restricted address for the NAND memory device, then the method allows the write command to modify the contents; and if the destination address is a restricted address for the NAND memory device, then the method prevents assertion of the write command on the contents.