NAND Flash Metadata Storage Using Phase Change Memory

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Solution Overview

Problem

NAND flash memory systems face performance limitations due to the time-consuming process of accessing and writing metadata and error correction codes to spare areas, which slows down write operations and lacks effective power loss recovery capabilities.

Innovation Solution

Implementing a NAND flash translation layer (FTL) that writes metadata and markers to a faster nonvolatile memory type, such as phase change memory (PCM), in parallel with writing data to NAND memory, thereby improving write speeds and enabling power loss recovery by separating data and markers from the main data storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metadata and error correction codes are written to spare areas of NAND flash memory, then data integrity is ensured, but write operation speed decreases

Engineering Contradiction:
Improvedata integrityVSAvoidwrite operation speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the metadata storage function by separating it from the main NAND flash memory. Metadata and error correction codes are stored in a dedicated buffer memory (separate from the main storage array), allowing data writing to proceed without waiting for metadata to be written to spare areas, thus resolving the speed-integrity tradeoff

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a buffer memory as an intermediary component between the host system and the NAND flash memory. This buffer temporarily holds metadata and error correction codes, decoupling the write speed of the main storage from the slower metadata writing process to spare areas

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If all data and metadata are stored in the same NAND flash memory array, then device complexity is reduced, but power loss recovery capability is lost

Engineering Contradiction:
Improvestorage structureVSAvoidpower loss recovery
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the storage system into distinct components: main NAND flash memory for data and a separate buffer memory for metadata and error correction codes. This physical separation enables independent management of data and metadata, allowing power loss recovery mechanisms to function effectively by preserving critical metadata in the buffer

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The buffer memory preliminarily stores metadata and error correction information before final commitment to the NAND flash memory. This preliminary storage ensures that if power is lost during the write process, the metadata remains intact in the buffer and can be used for recovery, preventing data corruption

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9152559B2Metadata storage associated with wear-level operation requests
Publication Date: 2015.10.06 MICRON TECHNOLOGY INC
  • US9152559B2 patent drawing
  • US9152559B2 patent drawing
  • US9152559B2 patent drawing

AI summary

A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.