3D NAND Flash Memory Mode Select Transistor with Ambipolar Contacts
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Solution Overview
Problem
The challenge in downscaling NAND flash memory devices is exacerbated by narrow refresh margins and increased read times due to the 3D NAND flash array's I-V curve characteristics, which hinder the improvement of operating speed.
Innovation Solution
A data storage device with a semiconductor structure incorporating a mode select transistor and ambipolar contacts, allowing for diode-type and field-effect transistor-type operating mechanisms, enhancing I-V characteristics and operating speed by controlling charge flow based on gate electrode voltage polarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D NAND flash array structure is used to enable downscaling, then integration density is improved, but I-V curve characteristics deteriorate resulting in narrow refresh margin and increased read time
Solution Approach 1:
The patent applies dynamics by making the memory device operable in two different modes (first mode and second mode) through voltage control. The mode select transistor dynamically switches between diode-type operation and field-effect transistor-type operation based on applied voltage polarity, allowing the system to adapt its operating characteristics rather than being fixed in a single state
Solution Approach 2:
The patent changes the operating parameters by utilizing ambipolar contacts that can operate with both positive and negative voltage polarities. By changing the voltage polarity and magnitude, the device transitions between different operating modes with distinct I-V characteristics, effectively changing the electrical parameters to optimize performance for different operations
2Ease of manufacture
If conventional 2D memory cell array architecture is downscaled, then manufacturing cost is reduced, but sensing margin deteriorates and disturbance between memory cells increases
Solution Approach 1:
The patent transitions from conventional 2D memory cell array architecture to a 3D stacked architecture where memory layers are vertically stacked. This dimensional change allows higher integration density while maintaining adequate sensing margins through the unique I-V characteristics enabled by the ambipolar contacts and mode-select transistor configuration
Solution Approach 2:
The patent implements multi-functionality through the mode select transistor that can operate in two distinct modes. The first mode provides one set of characteristics while the second mode provides another, allowing the same hardware structure to serve multiple operational requirements and optimize both sensing margin and integration density
3Speed
If mode select transistor with ambipolar contact is added to enable two-type operating mechanisms, then operating speed is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the mode select transistor structure. The ambipolar contact serves dual purposes by enabling both diode-type and field-effect transistor-type operation, and the mode select transistor itself performs both selection and mode-switching functions, reducing the need for separate dedicated components for each function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the operating speed and durability of NAND flash memory devices by expanding applicability through ambipolar contacts, enabling efficient charge flow and reducing unnecessary programming or degradation.
Implementation Method 1
The first contact may be an ohmic contact and the second contact may be a Schottky contact
Implementation Method 2
The first contact may be an ohmic contact and the second contact may be a Schottky contact
Implementation Method 3
a mode select transistor including a gate electrode and an insulation layer, the gate electrode being aligned with the neighbouring portion of the semiconductor region
Implementation Method 4
a plurality of memory cell transistors including a plurality of control gate electrodes and a data storage layer, the plurality of control gate electrodes being aligned with the semiconductor region, the data storage layer being interposed between the plurality of control gate electrodes and the semiconductor region
Data Source
AI summary
A data storage device includes a semiconductor structure including a first conductive-type region having a first-type conductivity, a second conductive-type region spaced apart from the first conductive-type region and having a second-type conductivity opposite to the first-type conductivity, and a semiconductor region between the first conductive-type region and the second conductive-type region and including a neighboring portion adjacent to the second conductive-type region; a mode select transistor including a gate electrode aligned with the neighboring portion and an insulation layer between the gate electrode and the neighboring portion; a plurality of memory cell transistors including a plurality of control gate electrodes aligned with the semiconductor region, and a data storage layer interposed between the plurality of control gate electrodes and the semiconductor region; a first wire electrically connected to the first conductive-type region; and a second wire including an ambipolar contact having a first contact between the second wire and the second conductive-type region, and a second contact between the second wire and the neighboring portion.