Integrated NAND-MRAM Memory Dies for Density and Cache Speed
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in achieving high performance, low power consumption, and high-speed data caching while scaling to meet demands for high-resolution image recording and data-intensive applications, particularly in wearables, electric cars, aircrafts, spacecraft, and data centers, with limitations in memory density and operating speeds.
Innovation Solution
A monolithic integration of NAND and MRAM dies with control circuits in a single semiconductor package, utilizing a network-on-chip communication system and error correction circuits, along with a memory controller, to enhance data storage and caching capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D NAND scaling is used to increase memory density, then memory density is improved, but data cache and operating speeds are limited
Solution Approach 1:
The patent combines 3D NAND die and 2D NAND die in a single semiconductor package, allowing the 3D NAND to provide high density storage while the 2D NAND serves as high-speed cache, thus resolving the contradiction between memory density and operating speed by merging different memory technologies
Solution Approach 2:
The patent segments the memory system into distinct functional components: 3D NAND die for high-density storage, 2D NAND die for high-speed caching, and control die for management, allowing each segment to optimize for its specific function rather than requiring a single technology to fulfill all requirements
2Quantity of substance
If memory scaling is pursued to meet customer demands, then memory density is improved, but read latency and write latency are increased
Solution Approach 1:
The patent implements a data caching mechanism where frequently accessed data is pre-loaded into the 2D NAND cache die before being needed by the host, reducing read latency by having data ready in advance. The control die manages this preliminary action by predicting and pre-fetching data to the cache
Solution Approach 2:
By merging 3D NAND (high density) with 2D NAND (low latency) in a unified package with integrated control circuits, the system achieves both high memory density and low read/write latency simultaneously, as the control die can route operations to the appropriate memory type based on performance requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high-speed, high-density non-volatile data storage with improved scalability and power efficiency, supporting advanced applications by optimizing read latency and write latency.
Implementation Method 1
one or more magnetoresistive random-access memory (MRAM) dies and one or more control dies positioned in a same semiconductor package
Data Source
AI summary
A memory system comprises a monolithic integration of a NAND die, a MRAM die and one or more control dies positioned in a same semiconductor package for high speed and high density non-volatile data storage. The MRAM die can be operated as a cache for the NAND die or to provide long term data storage for data not cached for the NAND die. In one embodiment, the NAND die comprises a plurality of NAND strings. The MRAM die comprises a MRAM structure. The one or more control dies comprise one or more control circuits for operating the NAND die and the MRAM die.