Multi-stage Data Compaction in NAND Memory
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Solution Overview
Problem
Existing data compaction techniques in NAND memory systems require significant overhead and consume limited SLC erase block resources, while also being inefficient in using the memory controller's data buffer.
Innovation Solution
A two-stage data compaction process is implemented, where valid data is first programmed into a destination erase block at two bits per memory cell in the first stage, and then additional valid data is programmed at two additional bits per memory cell in the second stage, eliminating the need for SLC blocks and optimizing data buffer usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If valid data is first programmed to SLC erase blocks before moving to MLC destination blocks, then data compaction can be performed, but system overhead increases and SLC erase block resources are consumed
Solution Approach 1:
The patent extracts the intermediate SLC block step from the data compaction process. Instead of using SLC blocks as temporary storage, the system directly programs valid data from MLC source blocks to MLC destination blocks, eliminating the need for SLC resources and reducing system complexity while maintaining data compaction functionality
Solution Approach 2:
The patent makes the destination MLC blocks serve dual purposes: they act as both the final storage location and the temporary holding area during the compaction process. By programming data at reduced density first (two bits per cell) and then completing the programming (four bits per cell), the system eliminates the need for separate SLC blocks while achieving the same compaction effect
2Ease of operation
If valid data is read into memory controller buffer before compacting, then data can be moved to destination erase block, but data buffer usage increases
Solution Approach 1:
The patent performs preliminary programming of valid data directly into the destination MLC blocks at reduced density (two bits per cell) before the final programming stage. This allows data to be moved and staged in-place within the memory structure itself, eliminating or reducing the need for large external buffer memory in the controller
Data Source
AI summary
Technology is disclosed herein for multi-stage data compaction. In a first data compaction stage valid data fragments from source erase block(s) are programmed into a destination erase block at two bits per memory cell. In a second data compaction stage additional valid data from the source erase block(s) is programmed into the destination erase block at two bits per memory cell. In this second stage, the same physical pages of memory cells in the destination erase block may be programmed such that each memory cell in the destination erase block is programmed to four bits.