NAND Memory Emulating NOR Boot Cache with Standalone Audio Playback

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Solution Overview

Problem

Existing memory devices, such as OneNAND and DiskOnChip, face challenges in data coherency and automatic address mapping when emulating NOR memory operations, and lack direct access capabilities, which hinder efficient power management and performance in portable computer systems.

Innovation Solution

A memory device that uses NAND flash memories to emulate NOR memory functions, incorporating a controller to manage data coherency and address mapping, allowing operation as a bootable BIOS, cache for hard disk drives, and standalone audio playback, even when the main processor is off or in hibernation mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If NAND flash memory is used to emulate NOR memory operations, then cost per bit of data is reduced, but data coherency management becomes more complex

Engineering Contradiction:

Improvecost per bit of dataVSAvoiddata coherency management

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The memory device performs automatic address mapping and data coherency management without requiring host intervention. The controller automatically handles the complexity of NAND emulation, making the system self-sufficient in managing data coherence between RAM buffer and NAND flash memory.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

A RAM buffer is introduced as an intermediary between the host and NAND flash memory. This buffer simplifies the interface to the host while automatically managing the complexity of NAND operations and data coherency, acting as a mediator that handles the problematic aspects of NAND emulation.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Extent of automation

If a controller is added to manage NAND memory operations, then automatic address mapping and data coherency are achieved, but device complexity increases

Engineering Contradiction:

Improveautomatic address mappingVSAvoidcontroller structure

Core Design Contradiction:

Extent of automationVSDevice complexity

Solution Approach 1:

The controller is designed to perform multiple functions including address mapping, data coherency management, and direct access to multiple processors. This multi-functionality consolidates what would otherwise require separate components, reducing overall system complexity while maintaining automation capabilities.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The controller integrates NOR flash memory, RAM buffer, and NAND flash memory control into a single device. This merging of functions into one unified controller reduces the number of separate components needed in the system, offsetting the internal complexity with external simplification.

Inventive Principle:

Principle #5Merging (Combining)

3Use of energy by moving object

If the memory device can operate independently without the main processor, then power consumption is reduced, but reliability of data access may be affected

Engineering Contradiction:

Improvepower consumptionVSAvoiddata access reliability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The controller includes status registers and interrupt capabilities that provide feedback to the host about the state of the memory device. This feedback mechanism ensures reliable data access even when operating independently, as the host can monitor and respond to the device status, maintaining system reliability while enabling low-power operation.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The memory device performs preliminary actions by maintaining readiness and being able to execute commands independently without requiring the main processor to be active. This allows the system to conserve power by keeping the processor in sleep mode while the memory device continues to function reliably.

Inventive Principle:

Principle #10Preliminary action

4Speed

If direct access to NAND memory is enabled, then access speed is improved, but the interface complexity increases

Engineering Contradiction:

Improveaccess speedVSAvoidinterface structure

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The RAM buffer acts as an intermediary that enables fast direct access to NAND memory while presenting a simplified interface to the host. The buffer absorbs the interface complexity of NAND operations, allowing high-speed access without requiring the host to deal with complex NAND protocols and timing.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS7519754B2Hard disk drive cache memory and playback device

Publication Date: 2009.04.14 RPX CORP

AI summary

A NOR emulating device using a controller and NAND memories can be used in a computer system in placed of the main memory or in place of the BIOS NOR memory. Thus, the emulating device can function as a bootable memory. In addition, the device can act as a cache to the hard disk drive. Further, with the addition of an MP3 player controller into the device, the device can function as a stand alone audio playback device, even while the PC is turned off or is in a hibernating mode. Finally with the MP3 player controller, the device can access additional audio data stored on the hard drive, again with the PC in an off mode or a hibernating mode. Finally, the device can function to operate the disk drive, even while the PC is off or is in a hibernating mode, and control USB ports attached thereto.